[gem5-users] Re: Functional read not implemented

Hi Vedika, That's bad luck and slightly surprising to me that functional reads are not implemented in Garnet. Because you use the SE mode, functional accesses are absolutely necessary for syscall emulation, both functional reads and writes. Now, why do Garnet only support functional writes? Acc

[gem5-users] Re: Functional read not implemented

BTW: the standard CHI.py configuration file does not seem to support Garnet anyway. You might want to use SimpleNetwork if you want CHI to work or change the protocol if you want Garnet to work. I don't have much experience with these other networks and protocols so I can't help you much on this

[gem5-users] Re: Functional read not implemented

Dear Gabriel, Thanks a lot for the information! I will try to implement the functional read function(s) and see how it goes. Thanks, Vedika. From: Gabriel Busnot via gem5-users Sent: 18 June 2021 13:46 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-us

[gem5-users] Re: Functional read not implemented

Also, could you let me know if this seems okay: As per 4th (Marc Orr) and 6th (Jason) replies in https://groups.google.com/g/gem5-gpu-dev/c/Wt43jSYYXag, the value returned by functional access gets overwritten with a value from the backing store, thus a functional read returning true always might

[gem5-users] CHI and caches

Hello I have been studying the CHI documentation and the configs/ruby/CHI.py file. Both the code and the documentation mention about 1) Map each CPU in the system to an RNF with private and split L1 caches 2) Add a private L2 cache to each RNF So what happens if the CPU model alread

[gem5-users] Re: Functional read not implemented

Well, you have likely set up a nasty time bomb here. What you are basically doing is assuming that - Valid data contained in the network is always present in a controller as well - Or the backing store data (memory) is up to date. Only in that case you can forget about the data in the network

[gem5-users] Re: Functional read not implemented

Wow thanks a ton for the advice! I'll definitely follow your guidelines. Thanks a lot, Vedika. From: Gabriel Busnot via gem5-users Sent: 18 June 2021 19:28 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: Functional read not implemented Well

[gem5-users] Re: Functional read not implemented

Hello, I think a relative patch is already commited (under review): https://gem5-review.googlesource.com/c/public/gem5/+/46900 Best, Polydoros On 6/18/21 5:22 PM, VEDIKA JITENDRA KULKARNI via gem5-users wrote: Wow thanks a ton

[gem5-users] Re: Functional read not implemented

That is a life-saver! Thanks! I will do the same for unmasked read as well along with masked. From: Polydoros Petrakis via gem5-users Sent: 18 June 2021 20:16 To: gem5-users@gem5.org Cc: Polydoros Petrakis Subject: [gem5-users] Re: Functional read not implemente

[gem5-users] Re: CHI and caches

Hi, O3_ARM_v7a_3 comes with predefined cache configurations that correspond to this specific CPU: O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, etc. However, these caches are effectively used only if CacheConfig.config_cache() is called. This does not happen if --ruby is used with the fs.py and se.py f

[gem5-users] Re: CHI and caches

Many thanks for the clarification, Gabriel. Best regards JO -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 18 June 2021 17:02 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: CHI and caches Hi, O3_ARM_v7a_3 comes with pre

[gem5-users] Error with gem5 full system simulation

Hello I followed the official documentation for running full system simulation for X86 architecture http://learning.gem5.org/book/part5/fs_config.html#running-full-system by executing the command: *build/X86/gem5.opt configs/tutorial_1/system2.py* I am getting an error : *Traceback (most rece

[gem5-users] Express snooping packet being queued during multi-threaded execution in SE mode?

Good Afternoon. I am running a custom benchmark in SE mode on x86 with multiple CPUs. The benchmark can be run with a varying number of worker threads. When I run the benchmark with only 1 thread everything works perfectly. However, once I use at least two threads, I get the following error messag

[gem5-users] [gem5 version 20.1.0.5] Writing to satp in RISCV FS mode causes error when L1 caches are added.

Hi, I'm working on an older version of gem5 (20.1.0.5), in which I run a RISCV full system simulation, I have added a minimal platform in this version of gem5 to run the FS simulation, but when I add cache hierarchy to the simulation the following error occurs after writing to the satp CSR. void

[gem5-users] Queued Ports

Hi all, Is there documentation for a conventional way to set up queued ports in custom memory objects? In learning_gem5, there is really good documentation for blocking ports, but the blocking port is currently a bottleneck in my application. Thank you in advance! Best, Sam _