cmd:./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color
DP1d_corr/trace.out
Processing trace... Traceback (most recent call last):
File "./util/o3-pipeview.py", line 379, in
main()
File "./util/o3-pipeview.py", line 371, in main
*(tick_range + inst_range))
File "./util
Maybe a python 2 vs 3 issue? I haven't used this script myself.
Gabe
On Mon, Apr 12, 2021 at 2:02 AM weiwei Zhao via gem5-users <
gem5-users@gem5.org> wrote:
> cmd:./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color
> DP1d_corr/trace.out
>
> Processing trace... Traceback (most recen
Hi,
Thanks for reporting this bug. It is indeed a python3 compatibility
issue, which is is addressed here
https://gem5-review.googlesource.com/c/public/gem5/+/7 and will be
merged to the develop branch soon.
Regards,
Hoa Nguyen
On 4/12/21, Gabe Black via gem5-users wrote:
> Maybe a python 2
Hi Chris,
Using Garnet or SimpleNetwork with Ruby will allow you to set the latency
of each link to anything you'd like and create any topology you'd like. You
should be able to configure this to model a multi-socket system. That said,
it's unclear if any of the current protocols will model a mode
Hi,
final_tick and sim_insts are RootStats (they are in src/sim/root.cc)
and they won't be reset by calling reset stats.
Regards,
Hoa Nguyen
On 4/11/21, kong han via gem5-users wrote:
> Hi all,
> Now I using the KVM CPU to run fs mode, and I try two ways to reset the
> m5out/stats.txt but all c
Hi,
Thank you for reporting this bug. The links have been updated!
Regards,
Hoa Nguyen
On 4/6/21, Ahmad SB via gem5-users wrote:
> Hi
> Links on https://www.gem5.org/documentation/learning_gem5 are not valid
> anymore (e.g.
> gem5.org/dist/current/gem5/cpu_tests/benchmarks/bin/arm/Bubblesort )
OK ^.^
Hoa Nguyen wrote:
> Hi,
>
> Thanks for reporting this bug. It is indeed a python3 compatibility
> issue, which is is addressed here
> https://gem5-review.googlesource.com/c/public/gem5/+/7 and will be
> merged to the develop branch soon.
>
> Regards,
> Hoa Nguyen
>
> On 4/12/21, Gabe
Hey Charlie,
I don't think there's any bug here. The debug out file is not one
instruction per line. Certain operations may be over two lines, for
example. We don't expect the number of lines in this file to equal the
number of simulated instructions so you can't compare these side-by-side.
Kind
Hey Majid,
The short answer is yes, this use-case should be supported.
You can use the `--restore-with-cpu` option to restore to the Atomic CPU.
Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616
web: https://www.bobbybruce.net
On Fri, Apr 9, 2021 at 2
Hi Nikolaos,
Thanks for bringing this to our attention. We are looking at this problem
here at Davis and will try to respond soon.
-Ayaz
On Sat, Apr 10, 2021 at 4:42 AM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:
>
> Dear Gem5 community,
>
> I try to add PCI interface in
Hi Aritra,
As you might have already noticed that there is a ptr to the data being
transferred (PacketDataPtr data) in the packet class:
http://doxygen.gem5.org/release/current/classPacket.html
I think you should be able to use methods like setData(), writeData() from
the same class to copy data
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