Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Andreas Hansson
Hi everyone, A bit of Saturday philosophising...you have been warned. All Discrete Event simulators that are used for SystemVerilog/SystemC/Verilog/VHDL etc (all describing inherently parallel behaviours) solve the problem "properly" by having delta cycles similar to the timebuffers in gem5. H

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Chen Tian
Thanks everyone for your reply. I have a better understanding but still have questions. Let's consider a time buffer B between two consecutive pipeline stages X and Y. When computing Y's output at cycle t, do we need the signal passed from X at t or t-1 (i.e., the struct in B with index t or t-1)?

Re: [gem5-users] Last leve cache accesses

2013-01-26 Thread Nilay
On Fri, January 25, 2013 10:30 pm, mihai pricopi wrote: > Hi, > > I would like to trace only the requests coming from lower level of caches > to the last level of cache indicating the cpu that made that request. I > used debug flag Cache but that contains too much information and I don't > know if

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Nilay
On Sat, January 26, 2013 12:01 pm, Chen Tian wrote: > Thanks everyone for your reply. I have a better understanding but still > have questions. > > Let's consider a time buffer B between two consecutive pipeline stages X > and Y. When computing Y's output at cycle t, do we need the signal passed >

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Chen Tian
Hi Nilay, I don't have any trouble understanding either the concept of a pipeline defined in any textbook or the implementation of SimpleScalar , or even the InOrder CPU model in GEM5 where you update a stage and notify an earlier stage at the same tick (so you go backwards). Just today when I loo

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Mitch Hayenga
"If both answers are t-1, which means the output of any stage only depends on some other stages' output at previous cycle, then I can understand why time buffer can get ride of the dependencies. However, if a stage requires a result from another stage at the same cycle, I cannot see how this works.

[gem5-users] (no subject)

2013-01-26 Thread SHARAN MORA (RIT Student)
Hi Everyone, How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot directly upgrade my gcc version 4.1.2 as I use Centos 5. Thanks, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

2013-01-26 Thread Fangfei Liu
Hi, you can add an environment variable CXX. For example, if you use bash, you can add a line in your .bashrc file: export CXX=g++44 Hope it helps. From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of SHARAN MORA (RIT Student) [sxm5.

Re: [gem5-users] Last leve cache accesses

2013-01-26 Thread mihai pricopi
In cache_imple.hh access() function, is the returned value of pkt->req->contextId() the id of the core who made the cache request (assuming no SMT) ? On Sun, Jan 27, 2013 at 5:45 AM, Nilay wrote: > On Fri, January 25, 2013 10:30 pm, mihai pricopi wrote: > > Hi, > > > > I would like to trace on

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Mitch Hayenga
Nilay, Stop talking down to this guy like he is someone without any understanding. Granted this email list gets a lot of "dumb" questions. But you jump to conclusions too fast and are too condescending to people on this email list. This guy is a PhD graduate with many publications ( http://www.

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Chen Tian
Thank you Mitch. I just came back to my computer after thinking through why the order of ticking pipeline stage does not matter with time buffer. Your email arrives in time. It confirms what I got and gives me more insights on the simulator design. I really appreciate it. Best, Chen On Sat, Jan 2

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Chen Tian
I have not spent much time in simulator before. However, my about 10-day experience with gem5 tells me that this simulator is great. It's very honorable to be part of the project or able to answer questions in the mailing list. Being polite in both asking and answering questions will certainly hel

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Nilay
On Sat, January 26, 2013 9:00 pm, Mitch Hayenga wrote: > Nilay, > > Stop talking down to this guy like he is someone without any > understanding. > Granted this email list gets a lot of "dumb" questions. But you jump to > conclusions too fast and are too condescending to people on this email > li

Re: [gem5-users] documents on O3 cpu implementation?

2013-01-26 Thread Chen Tian
> > level of discussion deteriorates so much that it makes me feel appalled. > This discussion thread is a case in point. > I am not sure how the discussion deteriorates so much until this point. I feel bad if anything makes you feel appalled, whether pipeline can be ticked in reverse order or