Hi,
How can I find which core send a message? As I read packet.hh, there
is no member like core_id or something else.
The only thing that I guess is
/**
* Device address (e.g., bus ID) of the source of the
* transaction. The source is not responsible for setting this
* field; it
Hi Mahmood,
Have a look at the MasterID.
The src/dest field is hop to hop and is only used by (de)multiplexing
components to send responses to the right port.
Andreas
On 25/01/2013 10:27, "Mahmood Naderan" wrote:
>Hi,
>How can I find which core send a message? As I read packet.hh, there
>is n
I see this in stride.cc
MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
However, on a single core simulation, I see that master_id is 6. How
that is possible?
On 1/25/13, Andreas Hansson wrote:
> Hi Mahmood,
>
> Have a look at the MasterID.
>
> The src/dest field is hop to hop and
Hi Mahmood,
You can ask the system what a specific master ID corresponds to (and get a
string back).
Each master in the system gets an ID. That includes DMAs etc. Thus, every
block that on its own generates requests should have a master id.
Good luck.
Andreas
On 25/01/2013 10:56, "Mahmood Nade
Sorry but I think I didn't get what you said
.
>You can ask the system what a specific master ID corresponds to (and get a
string back).
What I undesrtand is that I have to define a table that maps the
master id to a meaning full string. If that is true, then I have to
manually change the code and
On Thu, January 24, 2013 11:18 pm, Lu Hang wrote:
> I see. I miss-config the vmlinux binary path. The kernal can now booted
> up. However, there is also another issue coming up. There are two warn
> messages while simulating and it exits really fast. I'm not sure if the
> benchmark has finished run
On Thu, January 24, 2013 6:44 pm, Rodrigo Reynolds Ramírez wrote:
>
> I think my simulation finish satisfactorily, when it finishes I get this
> message:
> Exiting @ tick 3822080322000 because target called exit()
> and in both cases I get the same result in stats.txtsim_seconds
>
I am changing the latency of the simple memory in se.py, I changed the line in
this way:
first case:
physmem = SimpleMemory(range=AddrRange("512MB"),latency="1000ns")
second case:physmem = SimpleMemory(range=AddrRange("512MB"),latency="30ns")
I checked config.ini and the change is done but the r
Atomic or timing?
From: Rodrigo Reynolds Ram�rez
mailto:rodrigo.r...@hotmail.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Friday, 25 January 2013 12:26
To: gem5-users mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] About statistics
I am changing the latenc
I think I am using timing.
I compiled the simulator with:scons build/X86/gem5.opt
an run the benchmark using these command:./build/X86/gem5.opt
configs/example/se.py --caches --l1d_size=32kB --l1i_size=32kB --l2cache
--l2_size=256kB
--cmd=/scratch/rodri/spec2006/benchspec/CPU2006/403.gcc/run/r
Hello All,
I want to print current tick just before starting my benchmark. I use .rcS
scripts to run my benchmark after boot. I use dumpstats in my scripts for
periodically dumping stats. Is there any way to dump the current tick using
any existing utility? I tried a couple of things to print it.
I added the -s option to execution line, after include se.py and I see
differences into the execution time, I tried it with the helloWorld test. I
also tried gcc but after 3,5h the execution has not finished, is it normal?
without the -s option it takes around 1,5h but I don't have any performa
On Fri, January 25, 2013 9:06 am, Rizwana Begum wrote:
> Hello All,
>
> I want to print current tick just before starting my benchmark. I use .rcS
> scripts to run my benchmark after boot. I use dumpstats in my scripts for
> periodically dumping stats. Is there any way to dump the current tick
> us
Hi,
Is there any document on O3 implementation? I cannot get my head around the
logic where in each cpu tick, fetch stage is first ticked then decode ,
rename, iew and finally commit. I always thought it should be in reverse
order because an earlier stage in the same cycle does not know what
resou
I found the problem is that I compile the application on my 32-bit linux while
the kernel is 64-bit (which I did not notice in the beginning and then assumed
that 64 bit machine should be able to run 32 bit applications by nature )
So, the solution was to recompile the benchamrk with the option
On Fri, January 25, 2013 6:54 pm, Chen Tian wrote:
> Hi,
>
> Is there any document on O3 implementation? I cannot get my head around
> the
> logic where in each cpu tick, fetch stage is first ticked then decode ,
> rename, iew and finally commit. I always thought it should be in reverse
> order bec
On Fri, January 25, 2013 7:22 pm, Mostafa Mahmoud Hassan wrote:
>
> I found the problem is that I compile the application on my 32-bit linux
> while the kernel is 64-bit (which I did not notice in the beginning and
> then assumed that 64 bit machine should be able to run 32 bit applications
> by na
Nilay,
Ticking pipestages in reverse (and allowing values to propagate in that
order) is a *very* common way to implement processor simulators. I'd almost
call it the standard method. Though gem5 gets around this via the
timebuffer, other simulators do not use a timebuffer/pipe method. For
examp
Hi,
I would like to trace only the requests coming from lower level of caches
to the last level of cache indicating the cpu that made that request. I
used debug flag Cache but that contains too much information and I don't
know if it indicates who made the request.
Is there a debug flag for this
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