Hello,
Thank you Andreas for your reply.
I am able to find trace log for L1 and L2 cache.
Additionally, I am interested in similar trace for LLC/L3, i.e. I want to
find Read and Writes Hits, Misses to LLC/L3 as well.
My current Command Line Argument:
./build/ALPHA_ES/gem5.opt --quiet --outdir=r
Hi all:
I am so much wondering if I have to add much more DRAM to use gem5.opt.
My host workstation has:
16 GB DRAM
12 SMT cpu cores
The OS (64 bit RHEL 6) killed the gem5.opt which had been running "facesim"
(parsec, simmedium) for 2 days because the gem5.opt simulator used up even the
swa
Hi All,
I am trying to dig into Gem5 but I found it's fairly complicated. Can someone
give me any hint on how gem5 bring the concept of timing into those CPU models?
I can understand that each instruction is divided into several stages, but how
is the magic gem5 does to fetch the instruction in
absolutely right. Another way is:
-12bits for Tag---4bits to select
bank--8bits for index--6 bits for block offset
your way maps contiguous blocks across different banks of a cache, so this is
really helpful if processor is reading contiguous data fro
Hi all / Ali Saidi
What is missing here? Can explain anybody please?
I want to run /queens 16 on fs mode.
My Tracback
command line: ./build/ARM/gem5.opt configs/example/fs.py
--script=./configs/boot/queens.rcS
Traceback (most recent call last):
File "", line 1, in
File "/home/amine/Work
It sounds like there is a memory leak somewhere. Could you run it through
valgrind? You find a suppression file in the util dir.
Andreas
From: SUK CHAN KANG mailto:sckang...@yahoo.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Saturday, 24 November 2012 09:27
To: "ge
On Sat, 24 Nov 2012, Frank Yang wrote:
Hi All,
I am trying to dig into Gem5 but I found it's fairly complicated. Can
someone give me any hint on how gem5 bring the concept of timing into
those CPU models? I can understand that each instruction is divided into
several stages, but how is the m
Hello everyone,
In ruby_fs.py I try to connect cpu ports and ruby ports through
a coherent bus. I changed these two lines that connect the ports
directly:
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
to this:
cpu.tol1
On Sat, 24 Nov 2012, pushkar nandkar wrote:
Hi,
I am new to Gem5.
I am trying to implement a system in the SE mode. The system has 4 inorder
cpus. I have downloaded the Splash2 benchmarks and using those binaries.
I am using the se.py right now.
Here is the command line
./build/ALPHA/gem5.op
On Sat, 24 Nov 2012, zhengchl wrote:
Hi,
I implement a 1 level cache coherence protocol based on MOESI-CMP-directory,
and my protocol passes Ruby_random_test with max 16 cores and 1000 loads.
But I'm not sure those testes are enough, what should I do next to verify a
protocol?
You ca
On 11/24/2012 10:00 PM, Nilay Vaish wrote:
On Sat, 24 Nov 2012, zhengchl wrote:
Hi,
I implement a 1 level cache coherence protocol based on
MOESI-CMP-directory, and my protocol passes Ruby_random_test with max
16 cores and 1000 loads. But I'm not sure those testes are
enough, what shoul
Hello,
I was wondering if someone can help me. I used the << echo "export
M5_PATH=/home/pm/full_system_for_gem5/" >> ~/.bashrc >> but when I use <> all I see is <> in terminal and not the address I
specified in /.bashrc file. When I look in .bashrc I can see that the line has
added to file but
It's cycle approximate
On 24 Nov 2012, at 09:32, Frank Yang wrote:
> Hi All,
>
> I am trying to dig into Gem5 but I found it's fairly complicated. Can someone
> give me any hint on how gem5 bring the concept of timing into those CPU
> models? I can understand that each instruction is divided
I think the Ruby port might not send an addr range change on init as it
assumes it is connected to a CPU that does not care. The bus, however,
does.
Andreas
On 24/11/2012 13:52, "Pavlos Maniotis" wrote:
>Hello everyone,
>
>In ruby_fs.py I try to connect cpu ports and ruby ports through
>a coher
You can use "--kernal" in the command line to specify the path for your
kernel. See configs/common/Options.py for detail.
-Tao
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of pmo...@masonlive.gmu.edu
Sent: Saturday, November 24, 2012 10:31 AM
To: gem5-use
this is correct. However, there should be more tag bits for the purpose
of cache conherence and replacement (e.g., valid, dirty, LRU...)
-Tao
On 11/24/2012 01:23 AM, Nitin Chaturvedi wrote:
Dear sir
srry for wrong interpretation..please check again and correct
me if i am wrong
Nilay,
If you are using the same se.py that comes with the gem5, if there is only
one workload specified, All the system.cpu[i].workload is assigned the same
process.
However if I use the same se.py specifying the -c
"splash2/codes/kernels/radix/RADIX;splash2/codes/kernels/radix/RADIX;splash2/cod
Hi Pushkar,
According to my experience, you should create new liveprocess for each
(same) executive file. You can first use different benchmarks to see
whether the problem (segmentation fault) is still there. If not, then
you can come back to this special simulation: create new (empty)
livepr
On Sat, 24 Nov 2012, pushkar nandkar wrote:
Nilay,
If you are using the same se.py that comes with the gem5, if there is only
one workload specified, All the system.cpu[i].workload is assigned the same
process.
However if I use the same se.py specifying the -c
"splash2/codes/kernels/radix/RADI
Nilay,
This might be the issue. I am using the stable version from the repository.
I will download the latest version and check if it helps.
Tao,
I have attached the se.py.
please let me know if that is the correct way. I create a new liveprocess
for each workload.
Meanwhile I will download th
Thanks Tao, just one problem, when I use --kernel
"home/pm/full_system_for_gem5/disks" it adds the new address to previous one.
How can I delete the default address?
Thank you,
Parnian
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
You try to generate the multiprocesses in the SMT session (line
120--154). In this session, line 151 modified the numThreads to 4.
Therefore, each CPU assumes it has 4 threads (line 158). However,
definitely, you just assigned one workload to each CPU...
You can manually set numThreads to 1 an
I guess you have successfully set "M5_PATH" as the environment variable.
You don't need to remove this. Instead, you can adjust the "--kernel"
path accordingly.
Or, you can remove "M5_PATH" and everytime use the absolute path for
"--kernel".
-Tao
On 11/24/2012 11:10 AM, pmo...@masonlive.gmu
What do you think should I do to solve this problem? I use gem5
for about 1-2 months and there are many things that I cannot
understand yet! It's chaotic to me.
Pavlos
On Sat, 2012-11-24 at 15:33 +, Andreas Hansson wrote:
> I think the Ruby port might not send an addr range change on init as
I changed the destination address for kernel but still I get could not load the
kernel file.
Here is the whole thing:
pm@ubuntu:~/gem5$ sudo build/ARM/gem5.fast configs/example/fs.py
--disk-image=/home/pm/full_system_for_gem5/disks/arm-ubuntu-natty-headless.img
--kernel=/home/pm/full_system_fo
Kernel should be a file (e.g., vmlinux) but not a directory.
-Tao
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of pmo...@masonlive.gmu.edu
Sent: Saturday, November 24, 2012 11:57 AM
To: gem5-users@gem5.org
Subject: [gem5-users] can't load the kernel ( su
Tao,
Thanks for that,
It worked out!
I see the changes in the latest version(development repository) of se.py!
Thanks again. :)
Pushkar Nandkar
Graduate Student
Dept of Electrical Engineering
University of Minnesota, Twin Cities
On Sat, Nov 24, 2012 at 10:42 AM, Tao Zhang wrote:
> **
> You
I would think adding this to RubyPort::init() should do the trick:
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
(*p)->sendRangeChange();
}
If it works submit a patch to the review board.
Andreas
On 24/11/2012 16:56, "Pavlos Maniotis" wrote:
>What do you thi
Thanks Andreas but I got this fatal error:
fatal: Unable to find destination for addr 0x4000 on bus
system.cpu.tol1bus
On Sat, 2012-11-24 at 17:57 +, Andreas Hansson wrote:
> I would think adding this to RubyPort::init() should do the trick:
>
> for (CpuPortIter p = slave_ports.begin(); p
Hi,
Currently the classic memory system has a non-blocking cache which is
handled using MSHR and Write Buffer.
I want to implement a blocking cache and measure time/clock ticks for which
the CPU stalled. I am implementing a multicore system here.
Is there a way to implement that, like disabling t
Tao, I really appreciate your help. I tried with both arm.boot and vmlinux
still no change.
when I try vmlinix
I get:
info: kernel located at:
/home/pm/full_system_images/binaries/vmlinuz.arm.smp.fb.2.6.38.8
fatal: Could not load kernel file
/home/pm/full_system_images/binaries/vmlinuz.arm.sm
I am not familiar with ARM. I saw that you never specified the memory size
(by "--mem-size=512MB" ). Please add this in the command line and try again.
-Tao
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of pmo...@masonlive.gmu.edu
Sent: Saturday, November
On Sat, 24 Nov 2012, pushkar nandkar wrote:
Hi,
Currently the classic memory system has a non-blocking cache which is
handled using MSHR and Write Buffer.
I want to implement a blocking cache and measure time/clock ticks for which
the CPU stalled. I am implementing a multicore system here.
Is
My bad, the RubyPort also has to return an actual address range when the
bus calls getAddrRanges(). This is where it gets a bit tricky. I don't
have an easy and general solution. The port would have to know what the
memory range is.
Andreas
On 24/11/2012 18:10, "Pavlos Maniotis" wrote:
>Thanks
I'll try to find another solution to meet my needs.
Anyway, thank you very much for your help.
On Sat, 2012-11-24 at 21:52 +, Andreas Hansson wrote:
> My bad, the RubyPort also has to return an actual address range when the
> bus calls getAddrRanges(). This is where it gets a bit tricky. I do
Set both the number of MSHRs and the number of targets per MSHR to 1. If
you ONLY set the number of MSHRs to one, then you could have multiple
outstanding misses to the same cache line.
Amin
On Sat, Nov 24, 2012 at 3:30 PM, Nilay Vaish wrote:
> On Sat, 24 Nov 2012, pushkar nandkar wrote:
>
>
For anyone who would like to share one L1 cache among multiple cpus I
have found a possible solution that seems to work:
1) I modified the ruby protocol specific python config file (for example
MOESI_CMP_direcory.py in /gem5/configs/ruby) to create just one L1
cache, one controller and one sequenc
On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
For anyone who would like to share one L1 cache among multiple cpus I
have found a possible solution that seems to work:
1) I modified the ruby protocol specific python config file (for example
MOESI_CMP_direcory.py in /gem5/configs/ruby) to create ju
In /gem5/configs/ruby/MOESI_CMP_directory.py I changed this code:
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
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