Re: [gem5-users] Running PARSEC on GEM5

Did you run them all in x86, multi thread with ruby? I guess you should've edit the source code ... I'd appreciate if you post the disk image :) On Wed, Oct 31, 2012 at 5:34 PM, Runjie Zhang wrote: > I have successfully ran Parsec with recent version(changeset:01c8c5ff2c3b) > of Gem5 for both AL

Re: [gem5-users] Running PARSEC on GEM5

I did ran parsec in x86, multi thread with ruby without any modification to the source code. (Thanks to Marco Elver's great help!) Here are some details about disk images, binaries and linux kernel file that I used: - Pre-compiled X86 kernel: [http://www.cs.utexas.edu/~parsec_m5/x86_64-vmlinux-

[gem5-users] X86 multicore configuration files

Hello everybody, I successfully use gem5 FS mode with fs.py file. Are there any scripts ( examples ) for multicore environment? Thank you ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] L1, L2, L3 cache sizes not being used?

Hello, I am running gem5 in syscall emulation mode and specifying the cache sizes. This appears to work as desired. bpayne@bpayne-VirtualBox64:~/gem5$ build/X86/gem5.opt configs/example/se.py --clock=2.8GHz --l1d_size=32K --l1i_size=32K --l2_size=256K --l3_size=8192K -c tests/test-progs/hello

Re: [gem5-users] validation of x86

Here is an update for anyone who was wondering how to compare a real computer to the gem5 simulator. The L1i (instruction), L1d (data), L2, L3 cache sizes can be determined in linux by bpayne@bpayne-Alien:~$ cat /sys/devices/system/cpu/cpu0/cache/index0/type Data bpayne@bpayne-Alien:~$ cat /sys

Re: [gem5-users] L1, L2, L3 cache sizes not being used?

You seem to be running without caches. Try --caches and --l2cache Andreas On 01/11/2012 19:36, "Payne, Benjamin" wrote: >Hello, > >I am running gem5 in syscall emulation mode and specifying the cache >sizes. This appears to work as desired. > >bpayne@bpayne-VirtualBox64:~/gem5$ build/X86/gem5.

Re: [gem5-users] L1, L2, L3 cache sizes not being used?

Those options are being ignored because you're not using caches at all. You need --caches. -Tony On Thu, Nov 1, 2012 at 3:36 PM, Payne, Benjamin wrote: > Hello, > > I am running gem5 in syscall emulation mode and specifying the cache > sizes. This appears to work as desired. > > bpayne@bpayne-V

[gem5-users] getting large power consumption for a core

Hi all, For getting the power data for a core, I have fed McPAT tool with stats.txt file. The output I get from McPat shows that the power consumption (which is known as Runtime Dynamic) per core is very large whereas I want the power consumption (per core) to be less than 1 Watt. Does anybod

[gem5-users] memory bandwidth

Hi How can I calculate the PhysicalMemory bandwidth? Is that infinite in gem5? -- Regards, Mahmood ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] L1, L2, L3 cache sizes not being used?

With your suggestions, the syscall emulation works as desired when the cache sizes are specified: bpayne@bpayne-VirtualBox64:~/gem5$ build/X86/gem5.opt configs/example/se.py --clock=2.8GHz --caches --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=256kB --l3_size=8192kB -c tests/test-progs/he

Re: [gem5-users] validation of x86

Correction to both use of cache and units for cache size: bpayne@bpayne-VirtualBox64:~/gem5$ build/X86/gem5.opt configs/example/se.py --clock=2.8GHz --caches --l1d_size=32kB --l1i_size=32kB --l2cache --l2_size=256kB --l3_size=8192kB -c tests/test-progs/hello/bin/x86/linux/hello -Original Me

[gem5-users] Checkpoint restoration for ALPHA InorderCPU SEG FAULTS

Hello, ALPHA InorderCPU works fine (without checkpointing) in SE mode with Ruby. However, when I try to restore the checkpoint taken with TimingCPU (using MOESI_hammer ruby protocol) and restore it with Timing CPU but switch to InorderCPU I get a SEGFault. Here are the commands I am using to cr

Re: [gem5-users] Checkpoint restoration for ALPHA InorderCPU SEG FAULTS

A correction in the command to take the checkpoint, the command used to take a checkpoint is: ./build/ALPHA_MOESI_hammer/gem5.fast configs/spec2006/spec2006.py astar astar astar astar astar astar astar astar -n 8 --cpu-type=timing --l1i_size=32kB --l1d_size=32kB --l2_size=2MB --num-l2caches=32 --c

Re: [gem5-users] Checkpoint restoration for ALPHA InorderCPU SEG FAULTS

On Thu, 1 Nov 2012, Jagadish Kotra wrote: A correction in the command to take the checkpoint, the command used to take a checkpoint is: ./build/ALPHA_MOESI_hammer/gem5.fast configs/spec2006/spec2006.py astar astar astar astar astar astar astar astar -n 8 --cpu-type=timing --l1i_size=32kB --l1d_

Re: [gem5-users] Checkpoint restoration for ALPHA InorderCPU SEG FAULTS

Hello Nilay, Yes, I could see Ruby being used while checkpointing. When I use the flags "--debug-flags=ProtocolTrace,RubyGenerated" to confirm the same, I see the debug output containing the state transitions which look like: 66240500: system.dir_cntrl2: [Directory_Controller 2], Time: 132481,

Re: [gem5-users] memory bandwidth

If you use a recent version of gem5 the SimpleMemory has a bandwidth parameter. I would suggest using the DRAM controller model, SimpleDRAM and configure the timing accordingly. Andreas On 01/11/2012 20:52, "Mahmood Naderan" wrote: >Hi >How can I calculate the PhysicalMemory bandwidth? Is that

Re: [gem5-users] Checkpoint restoration for ALPHA InorderCPU SEG FAULTS

On Thu, 1 Nov 2012, Jagadish Kotra wrote: Hello Nilay, Yes, I could see Ruby being used while checkpointing. When I use the flags "--debug-flags=ProtocolTrace,RubyGenerated" to confirm the same, I see the debug output containing the state transitions which look like: Looking at the code fo

[gem5-users] Internship opportunity at AMD

AMD Research is looking for talented students for Spring internships. Candidates should have a strong background in computer architecture, especially in out-of-order cores. Experience with the gem5 x86 ISA implementation--that is, experience working with the ISA description and microcode--is req