BBench is a web-page rendering benchmark, however, it shouldn't interact
with the web-pages in any way. It's doing a google search for something
called ewbay and the keyboard is open, that shouldn't happen. Were you
interacting with the vncviewer with the mouse? Is it possible that this
query could
I see, probably I had some interacting with vncviewer with the mouse when the
keyboard is open. I tried to run the benchmark again and now it can run to
completion. Thank you very much for your kind help!
I have another problem. I took a checkpoint after booting the OS in atomic mode
with the d
Did you take a checkpoint with caches? If so, you must take a checkpoint
without caches.
-Tony
On Sun, Sep 30, 2012 at 2:58 PM, Fangfei Liu wrote:
> I see, probably I had some interacting with vncviewer with the mouse
> when the keyboard is open. I tried to run the benchmark again and now it
>
I didn't use caches when taking a checkpoint. This is the command line I used
to take the checkpoint.
build/ARM/gem5.opt --outdir=bbench configs/example/fs.py -b bbench-gb
--kernel=vmlinux.smp.mouse.arm --frame-capture --checkpoint-dir=bbench
From: gem5-users
You will need to use gdb or a similar tool to find out where that seg fault
is coming from.
-Tony
On Sun, Sep 30, 2012 at 3:29 PM, Fangfei Liu wrote:
> I didn't use caches when taking a checkpoint. This is the command line I
> used to take the checkpoint.
>
> build/ARM/gem5.opt --outdir=bbench
Hi All,
I want to configure a system with multiple CPUs with private L1 and L2
cache with classic memory (not RUBY). Also I don't want to have a
shared L3, so that means all L2 connect to the system memory bus. I've
read this thread
(http://www.mail-archive.com/gem5-users@gem5.org/msg0258
I've used private L2 caches with the classic memory model. You should only
need to modify the CacheConfig.py file to create separate L2's and busses,
then connect them to their respective cores and to the membus.
-Tony
On Sun, Sep 30, 2012 at 3:41 PM, wrote:
> Hi All,
>
> I want to configure a
Hi Anthony,
Thanks for your quick reply. Okay so basically, I only need to create
a bus between the L1 and L2 for all cores and then connect all the L2
cache to the membus right? Do you mind sending me your CacheConfig.py
just to make sure I won't make any mistakes.
Thanks
Quoting Antho
Hi,
This is the information I got from running it in gdb:
Switch at curTick count:1
info: Entering event queue @ 19318968082000. Starting simulation...
gem5.opt: build/ARM/sim/simulate.cc:66: SimLoopExitEvent* simulate(Tick):
Assertion `curTick() <= mainEventQueue.nextTick() && "event sched
I tried several different configurations. It works in atomic mode even with
caches. But segmentation fault occurs for both arm_detailed and detailed cpu
type. The checkpoint is taken in atomic mode. Should the checkpoint be taken
with the same cpu type as it runs by restoring the checkpoint?
Could you get a back trace when it happens. It's not a segmentation fault it's
a SIGABRT. You're running into a assertion and we need to know who is creating
this event that is causing you trouble.
Ali
On Sep 30, 2012, at 9:44 PM, Fangfei Liu wrote:
> I tried several different configuratio
Sorry I may use the wrong command when I run the executable with gdb to get
previous information. The problem I met is a little bit strange. I'm running
gem5 on a cluster. It turns out that it works fine at the head node of the
cluster with gdb (at least no segmentation fault after running for m
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