Hello
I also faced this problem. In my case it was caused by the fact that the
parameters at the system level (number_of_cores, number_of_L2s, number_of_NoCs
etc. in power.xml file) that had a value of 1 were not described afterwards in
detailed. If you post your power.xml file I can take a lo
Hi Xi,
The clock is a parameter of type Clock, and it is specified in terms of a clock
period in units of ticks internally. Hence, your setting as a frequency will
end up being printed as a clock period.
Hope it helps.
Andreas
From: gem5-users-boun...@g
Hi all,
I have run into this error when I have tried to update my working
repository:
Traceback (most recent call last):
File "/home/npremill/work/simulators/mygem5-test/util/style.py", line
464, in check_style
return do_check_style(ui, repo, **args)
File "/home/npremill/work/simulat
Dear all,
My investigations regarding this error
fatal: Unable to find destination for addr 0x21620f580 on bus system.membus
reveals that this error can be fixed by increasing the main memory size.
Verification:
1) I have defined a 8192MB memory such as
physmem = PhysicalMemory(range=AddrRange("81
Hi Andreas,
Thanks for the clarification. So when I set --clock in the command
line, the config.ini file prints clock period, is that right? That is
also explains why you cannot set more than 1GHz in Ruby network
frequency, because 1GHz is the smallest clock period or we can treat
it as base clock
Hi Nilay,
Sorry for late response, I din't check my emails since last night :).
Anyway, so the checkviolations part that we are talking about, that takes care
of not having any CMP violation of coherence, but it does not re-execute a load
(not at the front of the commit queue) and following yo
If you could post it for review it would be a lot easier to
understand since the email seems to have stripped all indenting.
Thanks,
Ali
On 13.07.2012 12:47, Dibakar Gope wrote:
> Hi
Nilay,
>
> Sorry for late response, I din't check my emails since last
night :).
>
> Anyway, so the che
Sure I will do that; let me see how can I make a diff file with all the changes
(changes need to be made to obey store-load ordering of a stronger model too!)
and post it for review.
Thanks,
dibakar
On 07/13/12, Ali Saidi wrote:
>
>
>
>
>
>
> If you could post it for review it would be a
Hi,
I'd like to boot a 03CPU on X86-FS, but the boot stops with the messages:
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
SMP alternatives: switching to UP code
Freeing SMP alternatives: 34k freed
--
On Fri, 13 Jul 2012, Anderson Faustino wrote:
Hi,
I'd like to boot a 03CPU on X86-FS, but the boot stops with the messages:
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
SMP alternatives: switching to UP code
Freein
To whom it may concern,
When I tried to compile and run x86 full system mode (referred to
http://www.mail-archive.com/gem5-users@gem5.org/msg00071.html and
http://www.mail-archive.com/gem5-users@m5sim.org/msg05271.html). I got the
following output:
command line: build/X86/m5.opt configs/example/f
11 matches
Mail list logo