Re: [gem5-users] compile Linux kernel for X86 FS

2012-07-12 Thread Lluís Vilanova
wael Amr writes: > Hi, > But i made Cd for the linux-2.6.28.4 > then i typed the command as shown : > make -C /Mac/gem5/linux-2.6.28.4 O=/Mac/gem5/linux-2.6.28.4 CC=gcc-4.4 > I got this error : > make: *** /Mac/gem5/linux-2.6.28.4: No such file or directory. Stop. > So is there anything missing

Re: [gem5-users] How to get IPC in FS mode

2012-07-12 Thread Nilay
On Thu, July 12, 2012 1:07 am, Xi Chen wrote: > Hi all, > > I have a question here, when I use SE mode to run SPEC 2006, the default > stats will give results like "system.cpu.ipc". While I use FS mode to run > some benchmarks like NetperfMaerts, it will only give > "system.cpu.numCycles" > and "sy

Re: [gem5-users] problem with read/write SYSFLAG register when caches turned on

2012-07-12 Thread Samuel Hitz
Ok I digged a little deeper now. The problem isn't the SYSFLAG register anymore, the second core gets booted. However I save right at the beginning the base of the .got section in r10. This is the instruction which achieves this 0x6401018 ldrr10, [pc, #16] ; 0x6401030 and this i

Re: [gem5-users] Problem with dma ports draining.

2012-07-12 Thread Ali Saidi
On 12.07.2012 02:45, Anthony Gutierrez wrote: > I've determined this is because drainEvent()->process() is being called when the port has properly drained. However, once it signals that it has drained, it gets another request. So the issue here isn't the tlb, but it's another component in the

Re: [gem5-users] problem with read/write SYSFLAG register when caches turned on

2012-07-12 Thread Ali Saidi
Did one of them save/read it with caches disabled? Ali On 12.07.2012 08:07, Samuel Hitz wrote: > Ok I digged a little deeper now. The problem isn't the SYSFLAG register anymore, the second core gets booted. However I save right at the beginning the base of the .got section in r10. This is

Re: [gem5-users] problem with read/write SYSFLAG register when caches turned on

2012-07-12 Thread Samuel Hitz
Yes the newly booted core reads it before caches get enabled. Shouldn't it be going to memory then instead? On Thu, Jul 12, 2012 at 3:15 PM, Ali Saidi wrote: > ** > > Did one of them save/read it with caches disabled? > > > > Ali > > > > On 12.07.2012 08:07, Samuel Hitz wrote: > > Ok I digged a

Re: [gem5-users] problem with read/write SYSFLAG register when caches turned on

2012-07-12 Thread Ali Saidi
that is an issue. One of them has the data in a core cache and the other is going to DRAM to get it. There are two options. (1) Map the storage location as uncacheable, so both cores always go to DRAM. (2) Implement the addrBootUncacheable() function in your system class (I assume you've got

Re: [gem5-users] problem with read/write SYSFLAG register when caches turned on

2012-07-12 Thread Samuel Hitz
Shouldn't it just work (it doesn't I tried) if I enable the caches before reading this location or is the cache virtually addressed? The problem with approach 1) and 2) is that the kernel gets dynamically loaded and relocated in memory so I don't know, which storage location I should map as uncach

Re: [gem5-users] How to get IPC in FS mode

2012-07-12 Thread Xi Chen
Hi Nilay, Thanks for answering the question. I tried to specify cpu-type in the command line and then directly got IPC stats from the file. Command line can be like this: ./build/ALPHA_MESI_CMP_directory/m5.opt configs/example/fs.py -b NetperfMaerts -I 1000 --cpu-type=detailed --caches Regar

Re: [gem5-users] Problem with dma ports draining.

2012-07-12 Thread Malek Musleh
So I have been following this thread as well since I too have an interest in getting this working. From the trace, it seems that the problematic request in this case is to address: 0x7ffc The ITLB Walker is unable to queue the read request, and so it needs to be retried > 5403272000: system.cpu.i

Re: [gem5-users] Problem with dma ports draining.

2012-07-12 Thread Anthony Gutierrez
You are right. The port is being "undrained" by the table walker. Using doDrain() instead of drain() gets past this problem. -Tony On Thu, Jul 12, 2012 at 9:14 AM, Ali Saidi wrote: > ** > > On 12.07.2012 02:45, Anthony Gutierrez wrote: > > I've determined this is because drainEvent()->process()

[gem5-users] Ruby frequency not working?

2012-07-12 Thread Xi Chen
Hi all, I have a question about the frequency of Ruby system. In Ruby system, the default frequency is 1GHz, which can be found at src/mem/ruby/system/RubySystem.py I use the command: ./build/ALPHA_MESI_CMP_directory/gem5.opt configs/example/ruby_random_test.py --num-cpus=16 --num-dirs=16 --top

Re: [gem5-users] Ruby frequency not working?

2012-07-12 Thread Xi Chen
Hi all, I tried another way to adjust the frequency. Set –clock= to 0.5GHz, 0.33GHz, 0.2GHz, then in the config.ini file the corresponding clock under “system.ruby” became 2,3,5. So the frequency adjustment does work, but the question is why set clock to 2,3,4 GHz, the system does not change an

[gem5-users] problem with gem5 and McPat

2012-07-12 Thread Bojun Ma
Hi, All, Any one has successfully integrated McPAT with gem5? I used m5-mcpat-parser to get the power.xml file. But when I used it as the input of McPAT. Always Error: The value of homogeneous_cores or number_of_cores is not correct! Any idea of how to debug it? I tra