It would be great to make this work. The key issue is that x86
synchronization is different from ARM & Alpha. The latter rely on
load-link/store-conditional, but x86 relies on the ability to do locked RMW
transactions that are guaranteed atomic. This is signaled to the cache
using the LOCKED flag
To correct myself, I ran a quick test and actually single-core does work
with this configuration, but the kernel crash happens with 2+ cores. I
prefer not to use Ruby due to the much slower simulation speed. I believe
this configuration (FS, multi-core, O3, classic memory) works with both ARM
and A
x86 multi-core with O3 and the classic memory system doesn't work, as the
classic caches don't have support for x86 locked accesses. In contrast,
x86 multi-core works with O3 and Ruby, since Ruby does support
locked accesses; and it also works with the AtomicSimple CPU model and
classic memory, si
I am simulating a multi-core system, but the issue also occurs with
single-core as well. The error message comes from the kernel. Here is one
of them below:
Thanks,
Ivan
Bad page state in process 'spec.astar_base'
page:807205e8 flags:0x mapping:00ba
mapcount:1
Sorry, we primarily use SE mode, so we don't have this problem. Is this
for a single-core system? Is the error message you see from the kernel or
from gem5?
Steve
On Sat, Jun 28, 2014 at 6:51 PM, Ivan Stalev via gem5-users <
gem5-users@gem5.org> wrote:
> Is anyone successfully running SPEC200
