rd.
>>
>> Thanks,
>>
>> Andreas
>>
>> From: Amin Farmahini
>> Reply-To: gem5 users mailing list
>> Date: Friday, 7 June 2013 21:54
>> To: gem5 users mailing list
>> Subject: [gem5-users] Some notes about SimpleDRAM controller
&
as
>
> From: Amin Farmahini
> Reply-To: gem5 users mailing list
> Date: Friday, 7 June 2013 21:54
> To: gem5 users mailing list
> Subject: [gem5-users] Some notes about SimpleDRAM controller
>
> Hi All,
>
> 1. In the SimpleDRAM controller, it is assumed tha
@gmail.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Friday, 7 June 2013 21:54
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Some notes about SimpleDRAM controller
Hi All,
1. In the SimpleDRAM controller, it is assu
Hi All,
1. In the SimpleDRAM controller, it is assumed that the DRAM burst size
equals to the cache line size. I think it makes more sense to use a
separate variable for burst size and get rid of bytesPerCacheLine. The
reason is that the DRAM controller could be connected (through a bus) to
caches
