Hi Harshil,
Thank you for providing the examples.
I tried util/tlm/conf/tlm_slave.py and it works. However, if I directly replace
TrafficGen with TimingSimpleCPU, simulation doesn't work.
Is there a better way to pass transactions to the TLM memory slave when using
TimingSimpleCPU as the CPU?
Hi Zitai,
In config_mem() in configs/common/MemConfig.py, commenting out the
following worked for me:
if opt_tlm_memory:system.external_memory =
m5.objects.ExternalSlave(port_type="tlm_slave",
port_data=opt_tlm_memory,
port=system.membus.mem_side_ports,
addr_ranges=system.me
Hi Zitai,
Here are some examples of using SystemC with gem5:
https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.py
https://github.com/gem5/gem5/tree/develop/util/tlm
However, it should be noted that the integration of SystemC with gem5 is
not being actively maintained by the commu
