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Cc: Nazmus Sakib
Subject: Re: [gem5-users] Re: Effective address and ISA
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On 2/6/2024 11:13 AM, Nazmus Sakib via gem5-users wrote:
I think gem5 has this SplitDataRequest() method that breaks the request if it
would need more than one cacheline.
In fact, the page fault is occurring before it goes to the cache. The panic message says the address is 0x400. By
looking in
I think gem5 has this SplitDataRequest() method that breaks the request if it
would need more than one cacheline.
In fact, the page fault is occurring before it goes to the cache. The panic
message says the address is 0x400. By looking into the disassembly and the
output log of -debug-flag=ExecA
On 2/5/2024 1:39 PM, Nazmus Sakib wrote:
I am trying to see how small I can set the cacheline size (gem5 ARM, test
binary is aarch64)
When I set it to 4 bytes, I get a page fault for address 0x400c00. By going through bunch of debugging (using print of
my own and debug flags), I think the probl
I am trying to see how small I can set the cacheline size (gem5 ARM, test
binary is aarch64)
When I set it to 4 bytes, I get a page fault for address 0x400c00. By going
through bunch of debugging (using print of my own and debug flags), I think the
problem is, when trying to generate address 0x4
On 2/5/2024 10:41 AM, Nazmus Sakib via gem5-users wrote:
Hello.
I was trying to find how the virtual (logical) addresses are calculated and
passed on to cpu.
In the load/store queee, after a request object is created, then the corresponding instruction is assigned a effective
address from this
