Hey Tang,
Have you found a way to work around this bug? I am also trying to integrate
DRAMsim3 as well, and would greatly appreciate any help.
Here is my error:
gem5.opt: build/X86/mem/dramsim3.cc:229: bool
gem5::memory::DRAMsim3::recvTimingReq(gem5::PacketPtr): Assertion
`wrapper.canAccept(pkt-
Dear gem5 community,I am trying to integrate DRAMsim3 with gem5, and I was able
to successfully build gem5 with DRAmsim3.And I can successfully use the full
system mode with AtomicSimple CPU. But when I use the TimingSimple CPU or
O3CPU, I can't get into the system.It reports a
bug:build/X86/si
