Hi all,
I’m keeping digging into how to config a shared L1 cache in ruby system. It
seams gem5 does not have safe method to do this in both classical and ruby
system. And I found some further problem which may help to config the shared L1
cache in ruby. And I want some help to make this right.
Hi Chao,
Yes, I had exactly the same error, when I was trying to switch CPU. You can
find the details from the link below.
http://www.mail-archive.com/gem5-users@gem5.org/msg10431.html
Unfortunately, currently I'm not digging into it, so do not know about this
problem.
Thanks,
Jae-Eon
2014년 9월
Hi Jae-Eon,
It begins to run now, after your suggestion.
But it goes to a CPU0 deadlock, which looks like following:
panic: Possible Deadlock detected. Aborting!
And according to its error information, there seams be some memory request
staved, and the deadlock checker is activated.
Have you
Hi Jae-Eon,
Thanks very much for your suggestion!
The method seams very attractive and helpful.
I’ll take it and tell the progress as soon as I get it.
Regards,
Chao
On Sep 18, 2014, at 1:39 PM, Jae-Eon Jo via gem5-users
wrote:
> I forgot to mention that you have to use MESI two level of Ru
I forgot to mention that you have to use MESI two level of Ruby, if you
want to follow my suggestion.
Thanks,
Jae-Eon
2014-09-18 14:33 GMT+09:00 Jae-Eon Jo :
> Okay.
>
> If I understood your plan exactly, I have an idea to implement this easily.
> As the implementation of CPU is decoupled from t
Okay.
If I understood your plan exactly, I have an idea to implement this easily.
As the implementation of CPU is decoupled from that of the memory system,
you will basically build 16-core system, but with the modification of port
assignment.
I'll just give an illustrative example of how it can b
Hi Jae-Eon,
You are right. I have just read the protocol files and it’s definitely not
trivial to modify the protocol implementation. But actually I got blocked when
I worked with the classical memory model to implement my cache connection
design.
I want a 2-core shared L1 and a 8-L1 shared L2
Hi, Chao,
As far as I know, each protocol of Ruby is tightly coupled with the memory
hierarchy.
That is, you should modify the protocol implementation
(src/mem/protocol/MESI_Two_Level*) to change the memory hierarchy, which is
not trivial.
My recommendation is to use the classic memory system (th
Hi all,
I’m working on ruby memory system. And I want to share a L1 cache for 2 cpu in
ruby cache system with MESI two level protocol. How to config it? Which part
should I work on? Thanks!
Chao.
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