Re: [gem5-users] Forcing Writeback of Dirty Cache Lines

2012-09-26 Thread Nilay Vaish
On Mon, 24 Sep 2012, z...@uwaterloo.ca wrote: Hi Nilay, Okay, if forcing the write back is not yet implemented. Then I want to at least know the number of dirty lines in cache at the end of simulation. How would I get this stat/parameter? Can you point me to the right source file if I need t

Re: [gem5-users] Forcing Writeback of Dirty Cache Lines

2012-09-24 Thread zpwu
Hi Nilay, Okay, if forcing the write back is not yet implemented. Then I want to at least know the number of dirty lines in cache at the end of simulation. How would I get this stat/parameter? Can you point me to the right source file if I need to add this myself. Many Thanks Quoting Nil

Re: [gem5-users] Forcing Writeback of Dirty Cache Lines

2012-09-24 Thread Nilay Vaish
On Fri, 21 Sep 2012, z...@uwaterloo.ca wrote: Hi All, How can I force writebacks of all the dirty cache lines after my program have finished running in the simulator. What I mean is that after the program finishes execution, the status of the last level cache will have some dirty cache lines

[gem5-users] Forcing Writeback of Dirty Cache Lines

2012-09-21 Thread zpwu
Hi All, How can I force writebacks of all the dirty cache lines after my program have finished running in the simulator. What I mean is that after the program finishes execution, the status of the last level cache will have some dirty cache lines and I want to force those cache lines to b