med Ghadimi
Reply-To: Hamed Ghadimi , gem5 users mailing list
Date: Thursday, 13 August 2015 07:04
To: "gem5-users@gem5.org"
Subject: [gem5-users] CPU and L1-d Cache Trace
Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all
the memory operation
ly-To: Hamed Ghadimi
mailto:hamed_ghad...@yahoo.com>>, gem5 users mailing
list mailto:gem5-users@gem5.org>>
Date: Thursday, 13 August 2015 07:04
To: "gem5-users@gem5.org<mailto:gem5-users@gem5.org>"
mailto:gem5-users@gem5.org>>
Subject: [gem5-users] CPU and L1-d C
Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all
the memory operation requests in the system.
I added following lines in the /src/cpu/BaseCPU.py file:
cpu.monitor = CommMonitor(trace_file='cpu.ptrc',trace_enable=True)
cpu.dcache_port = cpu.monitor.slave
cpu.mon
