[gem5-users] Multi-cycle Custom Instruction

Hi everyone, Do you have any ideas on how a custom instruction with multiple pipeline stages (like FP) can be implemented in Gem5? Basically, I need to implement a multicycle instruction with one-cycle throughput. Thank you! ___ gem5-users mailing list

[gem5-users] Segmentation fault when booting RISCV Linux on Gem5

Hi everyone, I want to run RISCV Linux on Gem5 FS modethe . I followed the instructions in this link (https://github.com/UCanLinux/riscv64-sample/tree/master) to build the Linux kernel, rootfs, and bbl. When I run this on Gem5, I can see the boot logs, but at the end of the bootloader, I get multi

[gem5-users] Question about running RISC-V program on Gem5

Hi everyone, I want to run a program built with RISC-V Linux toolchain (riscv64-unknown-linux-gnu-g++) on Gem5 and get its cycle count and other stats. I have two questions regarding this and would be thankful if you could help with them. 1. Can this program be run on Gem5 in SE mode? Or since

[gem5-users] Help with extending RISCV vector ISA

Hi everyone, For my project, I need to add a custom instruction to RISCV in Gem5 that loads 2 sets of 128 elements (32-bit float) from the memory, computes the dot product, and stores them back to the memory. A starting point is using the RISCV vector instructions, but I want to reduce the instru

[gem5-users] Gem5 Experiment: Which Stats Should I Check?

Hi everyone, I am currently running some experiments with Gem5 using the following processor configuration. In the stats file, I am seeing two sets of reports: one for switch0 and one for switch1. Does switch0 correspond to KVM? If so, I think I don't need to consider it as it is the stats for boo