[gem5-users] CommMonitor in Gem5

Does anyone use CommMonitor in Gem5? What is the trace format look like? Thanks. Victor From: Andreas Hansson To: Victor Ling ; gem5 users mailing list Sent: Wednesday, January 16, 2013 2:43 PM Subject: Re: [gem5-users] Gem5 and trace-driven simulation

Re: [gem5-users] Gem5 and trace-driven simulation

Hansson To: Victor Ling ; gem5 users mailing list Sent: Wednesday, January 16, 2013 2:43 PM Subject: Re: [gem5-users] Gem5 and trace-driven simulation Hi Victor, The TrafficGen module (in src/cpu/testers) supports trace replay. The trace format is the same as what the gem5 CommMonitor produces

Re: [gem5-users] Gem5 and trace-driven simulation

Hi Andreas, Thanks for the information. I am reading through the code to understand the TrafficGen. Greg From: Andreas Hansson To: Victor Ling ; gem5 users mailing list Sent: Wednesday, January 16, 2013 2:43 PM Subject: Re: [gem5-users] Gem5 and trace

[gem5-users] Gem5 and trace-driven simulation

Hi all,   Did anyone have experience to modifify Gem5 for trace-driven simulation? Can you please share your experience?   Since Gem5 is a event-driven simulator, I have a particular interest to study the memory behavior (coherency protocol, hot spot contention) using trace data file. Is the ide

Re: [gem5-users] Running Multocore Scheduler on Gem5?

From: Steve Reinhardt To: Victor Ling ; gem5 users mailing list Sent: Tuesday, October 9, 2012 5:33 PM Subject: Re: [gem5-users] Running Multocore Scheduler on Gem5? What kind of scheduler are you looking to support?  One very direct approach is just to run in full system mode, and

[gem5-users] Running Multocore Scheduler on Gem5?

Hi, I am doing the research on shared cache contention in multicore via scheduling. Does any have experience running a open source multicore scheduler on Gem5? Can you share your suggestion? I mean in terms of level of difficult. Use a real system would be easier but I don't have one handy. T

Re: [gem5-users] How to define Memory specification in Gem5?

Hi Andreas, Thanks for the info. When do you expect the DRAM controller model will be available? If it it going to take a while, is it possible for me to get an early release version for  testing? Thanks. Victor From: Andreas Hansson To: Victor Ling

[gem5-users] How to define Memory specification in Gem5?

Is there a way to specify a memory subsystem in Gem5? I plan to specify: - # of channel,  #Dimm/Channel, #of  rank/Dimm, #of bank/Rank - Mega transfers /second,  - Precharge time, row access time, column access time Thanks. Vic___ gem5-users mailing

[gem5-users] Gem5 and boot_emm.arm error

Hi, I am new to Gem5. I tried the following command but I got fatal: Could not read bootloader: /dist/m5/system/binaries/boot_emm.arm Any suggestion would be highly appreciated. Vic - Command: build/A