[gem5-users] Dumping stats into individual files

Hi, I am using gem5 se.py to run some simulations. Is there a simple way to dump the stats into different files each time I call m5_dump_stats(…)? I.e. I want the stats files to be organized as stats.1.txt, stats.2.txt, … instead of one monolithic stats.txt. Thanks! Subhankar Pal | PhD

Re: [gem5-users] Debugging std::bad_alloc memory errors in gem5

Thank you, Ciro. Turned out that by disabling most of the (classic) cache stat handlers, I was able to free up a lot of memory. Subhankar Pal | PhD Candidate, CSE | University of Michigan On March 25, 2020 at 4:38:52 AM, Ciro Santilli (ciro.santi...@gmail.com) wrote: I would try to put

[gem5-users] Debugging std::bad_alloc memory errors in gem5

t which memObject the allocation fails for? I have tried invoking gem5.opt with gdb, but I don’t get a backtrace, presumably because the failure happens in a Python function call. Thank for any help. Subhankar Pal | PhD Candidate, CSE | University of Michigan ___

[gem5-users] Zero cost print for debugging/profiling code in se.py

oes anyone have better suggestions? Thanks in advance! Subhankar Pal | PhD Candidate, CSE | University of Michigan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Spurious remote gdb connections

I will try it out. I appreciate the help. -- Subhankar Pal On April 20, 2019 at 4:40:41 PM, Pouya Fotouhi (pfoto...@ucdavis.edu) wrote: Subhankar, As Gabe mentioned, you should simply disable listeners (set --remote-gdb-port=0 with your gem5 binary) IF you are not inspecting your simulations

Re: [gem5-users] Spurious remote gdb connections

Could someone please help with this issue? -- Subhankar Pal On March 31, 2019 at 10:42:22 AM, Subhankar Pal (s...@umich.edu) wrote: Hi, I am running simulations on a modified se.py multi-CPU config on the Arm ISA. I am running custom benchmarks coded in C++. For some of my long-running

[gem5-users] Spurious remote gdb connections

: Couldn't read data from debugger. 1437182151000: system.remote_gdb: remote gdb detached 1438075461000: system.remote_gdb: remote gdb attached Please let me know if you have seen this before and/or have a solution. Thank you! -- Subhankar Pal | Computer Science & Engineering | Uni

[gem5-users] Running SPLASH-2 with Alpha on SE mode

your architecture"* >From a survey of previous posts in the mailing list, it seemed that m5threads is not supported for Alpha. Is it still the case, or is there a workaround for it? Thanks in advance. -- Subhankar Pal ___ gem5-users mailing li

[gem5-users] Mapping threads to CPUs in SE mode

ards, Subhankar Pal ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Device size vs. Address Range Assigned

Hi Muzamil, It probably means that the size of your memory divided by the number of memory devices is 256 MB, whereas the device_size of your memory is 8 MB. You need to make sure that these two number must be equal. - Subhankar On March 28, 2017 at 3:39:53 PM, Muzamil Rafique ( muzamil.ravian..

[gem5-users] Error while simulating GDDR5 memory

/dram_ctrl.cc:2107: void DRAMCtrl::Rank::processWakeUpEvent(): Assertion `(pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF)' failed.* Can someone help me on how to fix this error? Thank you! Subhankar Pal ___ gem5-users mailing

[gem5-users] Interfacing with HBM 2.0

Hi, I want to connect my system with 16 bidirectional 64-bit (~ x128 unidirectional) interfaces to an HBM 2.0 package. However, I could find the x128 interface definition only for HBM gen1 and not gen2 in src/mem/DRAMCtrl.py. Would it be correct to emulate an x128 HBM gen2 interface using the valu

[gem5-users] Disabling cache coherence

Hi, Is there an better way to turn off cache coherence in the classic memory model, than to hack the code in src/mem/cache/? I know that that there exists a noncoherent XBar model, but couldn’t find an equivalent for caches. Thank you! - Subhankar ___

Re: [gem5-users] Caches with interleaved address ranges connected to HBM

Yes, I'll do that. Thank you. Subhankar Pal On Mar 13, 2017 4:47 AM, "Andreas Hansson" wrote: Hi Subhankar, I think the best option would be to resolve any outstanding issues to properly support the AddrRange interleaving in the cache. It has definitely worked in the past, at

Re: [gem5-users] Caches with interleaved address ranges connected to HBM

, instead of using the interleave mechanism present in the C++ codebase. Can you tell me if that would work? Thank you! Subhankar Pal On March 11, 2017 at 1:43:16 PM, Andreas Hansson (andreas.hans...@arm.com) wrote: Hi Subhankar, Each cache has an address range, and it is by configuring these ranges

[gem5-users] Caches with interleaved address ranges connected to HBM

? Your help is highly appreciated! Subhankar Pal ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Simulating a multi-ported XBar-cache connection

go from XBar to cache and vice versa). How do I achieve this? Also, I would like to know how to simulate multiple channels in the main memory. Any pointers/explanation is highly appreciated. Thanks in advance for your help! Subhankar Pal | Computer Science & Engineering | Universit

[gem5-users] Simulating a multi-ported XBar-cache connection

go from XBar to cache and vice versa). How do I achieve this? Also, I would like to know how to simulate multiple channels in the main memory. Any pointers/explanation is highly appreciated. Thanks in advance for your help! Subhankar Pal ___ gem5-users