Hi Xing,
It seems to be a python script error to me. But, anyway I don't recommend
use DRAMsim2 in FS mode. DRAMsim2 is cycle-driven not event-driven. This
makes the FS simulation take unacceptably long time. The SimpleDRAM module
from Andreas should work for your project.
Best,
Xiangy
Hi Gabriel,
I have 4 patches in the gem5 review board. You can apply them if you want a
cache bank model (classic cache model only, not ruby).
Best,
Xiangyu
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Andreas Hansson
Sent: Friday, June 14, 2013
My modified code got an assertion error. I tried to debug it using the
--debug-flags feature. However, the previous assertion error was gone, and
I ended up with another assertion error in another place. I assume the
DPRINTF should not change any program running behavior. Anyone can explain
why
build problem
Hi Xiangyu,
As Matt said, my swig is too old (1.3.40). I just fixed the problem by
updating it to 2.0.9 (latest one).
Maybe the dependency on the official website should be updated
accordingly... http://www.gem5.org/Dependencies
-Tao
On 03/21/2013 01:00 PM, Rio Xiangyu Dong wrote
The root cause is that the new src/SConscript does not set up GCC
environment for version 4.4 correctly
if env['GCC']:
# Depending on the SWIG version, we also need to supress
# warnings about missing field initializers.
swig_env.Append(CCFLAGS='-Wno-missing-field
I think it's a very good finding. I also had the same issue (instant exit
after fast-forward when running multiple processes in SE) and I had a local
fix using the same idea (filter exit events that are labeled in one tick).
Tao, maybe you want to contact gem5-dev to add this patch, though I t
Hi all,
I'm trying to run PARSEC with native input on ALPHA FS. I used the PARSEC
binary files with self-checkpoint from the UT-Austin TR.
Though the checkpoint/restore scheme works find for some benchmarks like
blackscholes/canneal/dedup, I failed to restore the checkpoints generated by
s
True" too.
Tao
On 03/29/2012 05:12 PM, Rio Xiangyu Dong wrote:
Is this feature available on latest Gem5?
I tried to run a simple simulation out of box, but got the error message:
Traceback (most recent call last):
File "", line 1, in
File "/gem5/src/python/
Is this feature available on latest Gem5?
I tried to run a simple simulation out of box, but got the error message:
Traceback (most recent call last):
File "", line 1, in
File "/gem5/src/python/m5/main.py", line 357, in main
exec filecode in scope
File "configs/example/se.py"
While I was able to compile c++ source codes into ARM binary using GNU
Sourcery toolchain, I failed to compile ARMASM assembly to binary.
I used ARM RVDS 4.0 (armasm and armlink). Although I successfully got an ELF
file, the ELF file could not be read by Gem5. The error message I got was:
g
haven't tested ARM_SE. If
my benchmarks pass with ARM_SE in gem5.opt, that should narrow the source of
the problem down.
Thanks,
Andrew
On Tue, Mar 13, 2012 at 4:30 PM, Rio Xiangyu Dong
wrote:
I use gem5.opt, and never see this error.
From: gem5-users-boun...@gem5.org [mailto:gem5-u
ith your tests?
Thanks,
Andrew
On Tue, Mar 13, 2012 at 1:37 PM, Rio Xiangyu Dong
wrote:
Hi Andrew,
I didn't see this error in my simulations. May I ask which gem5 version you
are using? I find some of the latest code updates do not comply with my
changes. I am still using the
Hi Andrew,
I didn't see this error in my simulations. May I ask which gem5 version you
are using? I find some of the latest code updates do not comply with my
changes. I am still using the DRAMsim2 patch on Gem5 repo8643, and have run
all the runnable benchmarks in SPEC2006, SPEC2000, EEMBC2, a
Hi all,
After checking out the latest gem5 repo (repo 8818), I got running errors
when there is a cpu mode switch. I double-checked it with an old version
(repo 8737), and everything works fine. It seems to me that the new codes
might have bugs. Anyone got the same error?
Thanks,
Xiangy
Hi,
I'm trying to port PARSEC 2.1 benchmark to ARM_SE. I've statically
cross-compiled most of the benchmarks. Most of them can run smoothly.
However, the benchmark "ferret" encountered a error message of
"getrlimitFunc: unimplemented resource 7".
0: system.remote_gdb.listener: listening
It seems that bbench simulation on ARM_FS with Android Gingerbread OS does
not support Timing and O3 features.
I've tried
./build/ARM_FS/m5.fast configs/example/fs.py -b bbench -t
Got error message:
Global frequency set at 1 ticks per second
info: kernel located at:
/iceng
I've seen some unusual behavior when gem5 is simulating 4 processes on a
4-core configuration.
For example, the simulation exits after the fast-forward and reports
"Exiting @ tick xxx because a thread reached the max instruction count".
However, the program under simulation should still at leas
I am having a page table fault issue when running a benchmark on ARM_SE.
The error message I got was:
[.]
warn: mremapping to totally new vaddr 0x416ce000-0x41746000, adding 491520
warn: returning 0x416ce000 as start
warn: mremapping to totally new vaddr 0x41746000-0x4193c000, adding 2056192
Thank you for the quick response, Ali.
I wish I could just throw DRAM timing module away. However, my focus is
more on the memory access analysis, and I even integrated DRAMsim on
DRAMMemory for this purpose.
Do you have any other alternatives that I can do? Basically, I need a very
detailed ma
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