[gem5-users] 'm_stall_time' stat in MessageBuffer

Hi all, I am curious about the way *m_stall_time* stat is calculated in MessageBuffer. The *m_stall_time* is declared as statistics::Average, and MessageBuffer set the *m_stall_time* with the duration from enqueue to dequeue. At first, I thought this works like below: if three messages passed t

[gem5-users] Passing 2-dimension list from Python to C++ object

Hi all, For passing parameter to C++ object from Python, gem5 provides Param object. Through Param, int, float, string parameters can be passed to C++ object (Param.Int(), Param.Float(), Param.String(), etc) Now, I want to pass 2-dimension list from Python ([ [] ]), and get it as a vector> object

[gem5-users] Re: Garnet network stats

Thanks Srikant. Now, the stats is gathered normally after I increase the sim cycles as you said. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_n

[gem5-users] Garnet network stats

Hi all, I need to evaluate interconnect performance with garnet network, so I ran simulations with three configurations below. 1. Full-systsem with detailed CPU model (O3) 2. Full-system with functional CPU model (AtomicSimple) 3. Garnet synthetic traffic However, only FS with O3 CPU model outpu

[gem5-users] Cache hit/miss count in Ruby

Hi all, I am running full system simulation with MESI_Three_Level protocol. The protocol (maybe other protocol also) provides transition count for each state and possible events in stats file. For example, STATE.EVENT tells how many state transition occured from STATE receiving EVENT. Also, the st

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

Thanks Jason, Could you explain what other things should be considered for FLUSH if invalidate and write-back is not enough? Or is it fine modifying the CPU sequencer that it just ignores the FLUSH request? ___ gem5-users mailing list -- gem5-users@gem5.

[gem5-users] FLUSH request from CPU sequencer to cache controller

Hi all, I am running PARSEC benchmark with full system simulation. The CPU model is O3CPU (parameters tuned) with ARM ISA and MESI_Three_Level protocol were used. (build/ARM_MESI_Three_Level/gem5.opt) While the benchmark is running, panic occurs since the L0 cache controller gets unsupported type

[gem5-users] Question about MESI_Three_Level protocol

Hi all, I am making a system consisting of multiple CPU clusters using MESI_Three_Level. Since the MESI three level enable users to make multiple clusters, and each cluster can have multiple L2 caches, I just thought that L1 caches within the cluster can only access the L2 cache in the same cluste