ecial purpose,
>>> snooping is a better choice only for two cores.)
>>> This system is quite flexible in terms of memory hierarchy, so you can only
>>> modify the configuration scripts to achieve what you want.
>>>
>>> You will mostly modify two fi
modify a file under src
>> directory, you need to recompile gem5):
>> configs/common/CacheConfig.py (option parsing & shared L2)
>> src/cpu/BaseCPU.py (private L1's & port
>> connections)
>>
>> The current implementa
ify a file under src
>> directory, you need to recompile gem5):
>> configs/common/CacheConfig.py (option parsing & shared L2)
>> src/cpu/BaseCPU.py (private L1's & port
>> connections)
>>
>> The current implement
mentation has private L1 caches and shared L2 cache. To make
> L1 cache shared, you can refer to how L2 shared cache is configured.
>
> Thanks,
> Jae-Eon
>
>
> 2014-09-17 23:45 GMT+09:00 Chao Zhang via gem5-users :
> Hi all,
>
> I’m working on ruby memory system. An
Hi all,
I’m working on ruby memory system. And I want to share a L1 cache for 2 cpu in
ruby cache system with MESI two level protocol. How to config it? Which part
should I work on? Thanks!
Chao.
___
gem5-users mailing list
gem5-users@gem5.org
http://
Hi all,
I changed to the kernel provided by UT Texas. And it can support at least 32
cores.
Thanks a lot.
Chao
On Aug 28, 2014, at 10:09 PM, Chao Zhang via gem5-users
wrote:
> Hi Andreas,
>
> I tried the alpha first. I found I have set up this ISA and I rebuild it for
> this te
this problem
>
> I hope that explains it.
>
> Andreas
>
> From: Chao Zhang via gem5-users
> Reply-To: Chao Zhang , gem5 users mailing list
>
> Date: Wednesday, 27 August 2014 07:47
> To: gem5 users mailing list
> Subject: [gem5-users] How many cpu does the x8
hat does not have this problem
>
> I hope that explains it.
>
> Andreas
>
> From: Chao Zhang via gem5-users
> Reply-To: Chao Zhang , gem5 users mailing list
>
> Date: Wednesday, 27 August 2014 07:47
> To: gem5 users mailing list
> Subject: [gem5-users] How
Dear all,
I’m currently working on x86 FS on classical memory system to simulate cache
system. But I found the kernel booting just hangs before loading benchmark
script. It does not work when I set 3 or more x86 timing simple cpus, but it
does work when I set them as atomic cores. And it also w