[gem5-users] Re: Chiplet Simulation with Gem5

2024-02-22 Thread zhangcongwu--- via gem5-users
Hi Preet, There's a missing parameter in configs/ruby/Ruby.py:259 (maybe different, search makeTopology), you should add a `full_system` param to this method. The order of these parameters should be same as `makeTopology` in `KiteLarge_EWMC.py`. Best, Congwu Zhang From: Preet Derasari via gem

[gem5-users] Re: Can I use RiscvO3CPU with TSO?

2024-02-22 Thread Z HW via gem5-users
Hi Jason, Thanks for the response! Without knowing too much details about the O3 core, I replaced the frontend (i.e. the fetch unit) of the O3 with a customized instruction generator to directly exercise memory access sequences - this way I can isolate the impact of the instruction cache and make

[gem5-users] Re: Chiplet Simulation with Gem5

2024-02-22 Thread Preet Derasari via gem5-users
Hi Srikant, Thank you so much for answering my questions and providing the reference file. Since I am new to NoC simulation and using Garnet 3.0 (HeteroGarnet), I feel a little lost regarding running a SE or FS mode simulation. I checked the documentation on Gem5 posted ( https://www.gem5.org/do