Hello.
Is there a way, to change cacheline size for different level of cache ?
Example: L1 cacheline size is 64 byte and L2 is 128 bytes ?
If there is not a direct way (changing some parameter from python), what will
be the issues with building this ?
Things I know:
1. fetchbuffer size has to be
Hi everyone,
I have a requirement to dump traffic traces of running a program in gem5 and
replay it in another NoC simulator (e.g., Noxim). I have two questions, and any
help or pointers would be appreciated.
1.
I want to dump traces of every inter-node traffic (e.g., a read request from an
L
Hi everyone,
I have a requirement to dump traffic traces of running a program in gem5 and
replay it in another NoC simulator (e.g., Noxim). I have two questions, and any
help or pointers would be appreciated.
1.
I want to dump traces of every inter-node traffic (e.g., a read request from an
On 2/14/2024 1:14 PM, Eliot Moss via gem5-users wrote:
On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does
vary in each iteration, sometimes it is above 100. So I think it should be
the physical register value.
On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does
vary in each iteration, sometimes it is above 100. So I think it should be
the physical register value. If my understanding is correct, the physical
register
I would like to add some additional information. The register number does vary in each iteration, sometimes it is above 100. So I think it should be the physical register value.
If my understanding is correct, the physical register should be set during the IEW stage before the instruction is commi
On 2/14/2024 12:26 PM, reverent.green--- via gem5-users wrote:
Hey Eliot,
thank you for your answer. I have a follow-up question.
I know, that there are more physical registers than architectural ones and that the achitectural state should be set in
the final commit state.
So if the debug messag
Hey Eliot,
thank you for your answer. I have a follow-up question.
I know, that there are more physical registers than architectural ones and that the achitectural state should be set in the final commit state.
So if the debug message linked in my earlier mail shows e.g.: "Setting int register 54
On 2/14/2024 11:19 AM, reverent.green--- via gem5-users wrote:
Hello everyone,
can someone give me a hint, where exactly in the code the architectural state of (load) instructions is getting set and
becomes visible? I tried to trace instructions during the execution via log outputs, but got a bi
Hello everyone,
can someone give me a hint, where exactly in the code the architectural state of (load) instructions is getting set and becomes visible? I tried to trace instructions during the execution via log outputs, but got a bit lost during the IEW stage.
I know, that instructions, which
Sorry, can you post your code again, the file is no longer valid, thanks a lot!
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Hello,\
I would like to simulate hybrid memory through gem5,\
but when I execute the file configs/nvm/sweep_hybrid.py,\
I get the following message : Attribute reference on bound proxy
(Parent.clk_domain.getValue)\
attachment is my code
Thanks, best regards.
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