[gem5-users] Re: ARM SVE ISA

2024-01-14 Thread Nazmus Sakib via gem5-users
Thank you. I will try to switch to starter_se.py. I still had some questions regarding SVE. 1. When I compile with msve-vector-bit set to 512, I can see PTRUE instruction, which is replaced by whilelow when I compile without setting the vector bit value. Now on gem5, it seems whilelow and the cor

[gem5-users] Re: Spec2017 GCC benchmark crashes in SE mode

2024-01-14 Thread muke101 via gem5-users
Hi, thanks for the reply. Assuming that the page isn't being allocated when it should be, what could I do with this information? I'm not familiar with this part of the Gem5 codebase. Also, just to be clear, what do you mean by 'when the image download is done'? Thanks. Sent from Proton Mail mo

[gem5-users] Re: Spec2017 GCC benchmark crashes in SE mode

2024-01-14 Thread sun2k23 via gem5-users
Hi, I have ever met several similar issues but i'm not running Spec2017. I think that's because you use this address 0x66195c before allocating page firstly. You can enable the debug-flag of MMU to check whether the page related to this address is allocated when the image download is do