[gem5-users] X86 full system simulation---about m5term

2024-01-11 Thread hu miao via gem5-users
Hello everyone, I am new to gem5 and I have been trying to use gem5 for X86 dual-core full system simulation, following the steps in this tutorial: https://www.gem5.org/documentation/gem5-stdlib/x86-full-system-tutorial. However, I encountered some issues during the process. I am unable to use m5t

[gem5-users] Re?? About kvm-x86 in SE mode

2024-01-11 Thread ChenShixuan via gem5-users
Hi muke101, I followed the tutorial of Gem5 (using kvm) to add my user to the kvm and libvirt groups. And I have been running gem5 under root user all along. Thank you for your reply?? Original Message ??:

[gem5-users] Re: About kvm-x86 in SE mode

2024-01-11 Thread sx Chen via gem5-users
Hi muke101, I followed the tutorial of Gem5 (using kvm) to add my user to the kvm and  libvirt groups. And I have been running gem5 under root user all along. Thank you for your reply！ ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe se

[gem5-users] Re: About kvm-x86 in SE mode

2024-01-11 Thread muke101 via gem5-users
Might not be it but are you part of the KVM user group? Does it work if you run gem5 under sudo? Sent from Proton Mail mobile Original Message On 12 Jan 2024, 02:46, ChenShixuan via gem5-users wrote: > Hi all, > > I am a beginner to use the Gem5. I am using kvm to run "x86-hel

[gem5-users] About kvm-x86 in SE mode

2024-01-11 Thread ChenShixuan via gem5-users
Hi all, I am a beginner to use the Gem5. I am using kvm to run "x86-hello64-static" and switch to timing cpu in SE  simulation but it seems to be not working. And I am getting an error that I dont understand. Here are the errors that I am getting: ~~~ src/sim/simulate.cc:199: info: Entering

[gem5-users] How to Profiling Memory Access for Specific Malloc Data Structure In gem5?

2024-01-11 Thread wanli990802--- via gem5-users
Let's say I create two arrays A and B in my program, and these address space is kept unchanged during the execution of the program. How should I expose the addresses of these two arrays to gem5 and then profile the access information of these addresses in the cache of gem5. Any help would be gr

[gem5-users] Re: ARM SVE ISA

2024-01-11 Thread Nazmus Sakib via gem5-users
Not compiling with -msve-vector-bits did the trick. It runs perfectly, whether I set the cpu[0].isa[0].sve_vl_se to 4 or keep it to 1. Thank you for the suggestions !! One last thing, the starter_se.py does not seem to have support for --cpu-type=ArmO3CPU (or am I missing something) ? __

[gem5-users] Re: ARM SVE ISA

2024-01-11 Thread Giacomo Travaglini via gem5-users
Hi Nazmus, I can see from what you posted you are compiling the testcase with 512b vector width. I believe you should amend the gem5 VL accordingly… Basically writing up in the gem5 config: cpu.isa[0].sve_vl_se = 4 According to [1]. This should fix your problem. Another solution I believe woul

[gem5-users] ARM SVE ISA

2024-01-11 Thread Nazmus Sakib via gem5-users
Hello. I am trying to run a simple program with SVE instructions on gem5. However, the output with debug flag ExecALL suggests there is a issue with the decoder. Here is the test code: #define STREAM_ARRAY_SIZE 16 void main() { for (int j=0; j___ gem5-us

[gem5-users] About kvm-x86 in SE mode

2024-01-11 Thread 太阳王 via gem5-users
Hi all, I am a beginner to use the Gem5. I am using kvm to run "x86-hello64-static" and switch to timing cpu in SE  simulation but it seems to be not working. And I am getting an error that I dont understand. Here are the errors that I am getting: ~~~ src/sim/simulate.cc:199: info: Entering