[gem5-users] Re: Example for connecting Ethernet PCI device through ARM SMMU

Hi, Thank you for asking the question. This question is already in discussion on gem5 GitHub: https://github.com/orgs/gem5/discussions/239.I hope you find the answer to your question there. Regards, HarshilPatel On Mon, Aug 28, 2023 at 10:57 AM Chathura Rajapaksha via gem5-users < gem5-users@gem5

[gem5-users] Re: Prefetching during instruction decode

Thank you a lot for the reply. I tried looking into the prefetcher class in the mem folder, however I was still unable to figure out how to actually push the prefetch request. I am quite new to gem5, so I'm having a bit of extra trouble. Would you know of a way to send memory access requests in ar

[gem5-users] Re: Performance Discrepancy in gem5 Simulations Across RISC-V, x86, and ARM

Hi Daniel, You should see some minute differences in the total boot time for each of the ISAs. However here are some reasons why you're seeing this kind of difference in the boot times. I am assuming that you're using the default pre-built disk image resources from Gem5 Resources. The reason that

[gem5-users] Re: Lock implementation in Ruby Cache Memory and Request Queue

Hi, 1. First, isLocked is part of the implementation of atomics based on load-linked-store-conditional. When processing a request in ruby controllers, lines will not get blocked manually. In order to avoid request hasards, several mechanisms are available. 1. The block_on mechanism of peek.

[gem5-users] Performance Discrepancy in gem5 Simulations Across RISC-V, x86, and ARM

Hello, I would like to confirm whether the following observation is correct: Is the gem5 RISC-V simulation of riscv-ubuntu-20.04-boot approximately 30 times slower than the equivalent workload for x86 and aarch64? Or could there be an error in my setup? Scenario: I am booting a full-system simula