On 6/22/2023 8:19 PM, Khan Shaikhul Hadi via gem5-users wrote:
Hi,
Thank you for your response with the patch link. It helped me a lot to understand what's going on
and limitations with clflush.
Do you have any idea if clflush alternative for arm isa is implemented in gem5 properly or not. I
Hi,
Thank you for your response with the patch link. It helped me a lot to
understand what's going on and limitations with clflush.
Do you have any idea if clflush alternative for arm isa is implemented in
gem5 properly or not. I work on persistent memory and for x86 isa, you need
clflush and fenc
On 6/22/2023 5:47 PM, Khan Shaikhul Hadi wrote:
Hi Eliot,
Thank you for your detailed answer.
For my current work, I need "CLFLUSH" and "MFENCE" to work properly. For clflush, I was planning to
modify the instructions execution to issue a flush request to the cache and handle the rest using
dir
On 6/22/2023 4:54 PM, Khan Shaikhul Hadi via gem5-users wrote:
Hi,
I want to simulate a Persistent Memory machine in gem5. Gem5 has an NVMe module but at instruction
level ,for most part, it does not simulate CLFLUSH ( specially for MESI cache coherence protocol ).
I am also not sure if it simu
Hi,
I want to simulate a Persistent Memory machine in gem5. Gem5 has an NVMe
module but at instruction level ,for most part, it does not simulate
CLFLUSH ( specially for MESI cache coherence protocol ). I am also not sure
if it simulates memory fence properly (For out of order cpu, it seems like
MF
Hello Ayaz,
Thank you for your response! 😊
I am trying to checkpoint with Atomic then restore to atomic and switch to
Timing/O3.
Your advice works if I checkpoint with this and also with Timing, then restore
with Timing and switch, thank you.
From my knowledge the way to switch CPUs in stdlib
Hi Srikant,
I appreciate your assistance. If you could provide me with a sample topology as
a reference, that would be very helpful!
Many thanks!
Best regards,
Henry
From: Srikant Bharadwaj
Sent: 21 June 2023 19:58
To: The gem5 Users mailing list
Cc: Haoyu Wang
