[gem5-users] Re: SMT in full system mode

Can I use SMT with openMP? Eg, if I have 2 CPUs with SMT, the program runs with 4 threads? Thanks! On Fri, May 19, 2023 at 11:52 AM Ishita Chaturvedi wrote: > Hi Ayaz, > > Thank you for the link! > The problem here is twofold: > >1. > >The APIC id doesn’t take into account the SMT threa

[gem5-users] Re: SMT in full system mode

Hi Ishita, Regarding SMT in FS mode, you might find the discussion in the comments of the following JIRA issue helpful: [GEM5-332] SMT simulation in x86 is not supported - Jira (atlassian.net) -Ayaz On Thu, May 18, 2023 at 10:22 PM Ishita Chaturvedi

[gem5-users] SMT in full system mode

Hi, I want to run SMT in FS mode, however, the support does not exist for it. Is there a reason for this support to not be available? Is it easy to implement SMT in FS mode? Thanks! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send

[gem5-users] Re: Multi-level TLB is implemented in performance

Thanks for your email. I will look into the "multi-level TLB for Arm" implementation Wish you a good day Arun On Thu, May 18, 2023 at 9:25 PM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Just for the sake of completeness (I know Arun asked about X86). > There is a multi-level TLB f

[gem5-users] Re: Multi-level TLB is implemented in performance

Just for the sake of completeness (I know Arun asked about X86). There is a multi-level TLB for Arm; it is possible for other ISAs to implement the same, it requires a developer to move the translateAtomic/Timing methods from the TLB to the MMU Kind Regards Giacomo From: Jason Lowe-Power via g

[gem5-users] Re: Multi-level TLB is implemented in performance

There is not a multi-level TLB model in mainline gem5. Cheers, Jason On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users < gem5-users@gem5.org> wrote: > Hi, > Can anyone please tell me whether a multi-level TLB implementation is > currently available for x86? > > Thanks > Arun > > On We

[gem5-users] Re: Multi-level TLB is implemented in performance

Hi, Can anyone please tell me whether a multi-level TLB implementation is currently available for x86? Thanks Arun On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users < gem5-users@gem5.org> wrote: > Yes, this is possible, and I believe it's already implemented for Arm. > > The best p