Hi ,
I am new to gem5. I would like to know if I can run a machine-learning
model on gem5. Would gem5 accept external libraries like TensorFlow,
PyTorch..etc. please provide me with some first steps to approach this
problem of running a machine learning model on gem5.
regards
saras
_
Hi Zhang,
I wanted to add that you can check the Linux kernel booting log to see
whether the kernel recognized the maximum vector length of SVE correctly.
Note that even if the SVE vlen is correctly recognized by the kernel, it
doesn't mean the whole vlen is available to userspace. Though, I think
On 4/20/2023 12:20 PM, 中国石油大学张天 via gem5-users wrote:
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already
midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I
send you an email, you always reject it.
If y
Okay, thank you. I have received your suggestion and I will think it over
tomorrow. It's already midnight here, so I'll go to bed first ?9?6?? Thank you
again. By the way, it seems that every time I send you an email, you always
reject it.
-- --
?
Okay, thank you. I have received your suggestion and I will think it over
tomorrow. It's already midnight here, so I'll go to bed first ?9?6?? Thank you
again. By the way, it seems that every time I send you an email, you always
reject it.
-- --
??
Okay, thank you. I have received your suggestion and I will think it over
tomorrow. It's already midnight here, so I'll go to bed first ?9?6?? Thank you
again. By the way, it seems that every time I send you an email, you always
reject it.
-- --
?
Hi Giacomo,
Thanks for your birlliant reply, giving me some insights! But there are
some problems.
For the ZCR_EL register, I try to read or write the value from the register. I
try to use the inline assembly, I use msr instruction. Then use the g++
-march=armv8-a+sve option to compile the t
On 4/20/2023 11:56 AM, 中国石油大学张天 via gem5-users wrote:
Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to
design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in
Gem5. I'm not sure if it's feasible. I am so
Thank you for your reply again, hahahaha. I have been thinking recently whether
it is possible to design ALU through Verilog, translate it through Verilator or
other tools, and ultimately use it in Gem5. I'm not sure if it's feasible. I am
so obsessed with ALU because I need to provide a rough r
On 4/20/2023 11:33 AM, Eliot Moss via gem5-users wrote:
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, h
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is
this instruction executed?
gem5 does not model a
Hello everyone, I would like to ask, when executing non memory access
instructions in Gem5, shouldn't it be executed in ALU? But ALU has not been
specifically designed and implemented, how is this instruction executed?___
gem5-users mailing list -- gem5
Hi Zhang,
That parameter configures the *maximum* (hardware constrained) vector length.
It is possible to choose a different (smaller) vector length for a process by
configuring the following registers
ZCR_EL1 [1]
ZCR_EL2 [2]
ZCR_EL3 [3]
So I believe the problem is that while you are pro
Hi all,
Since gem5 is using python scripts to create configuration files. Is there any
way to create the configuration file without using the binary like gem5.opt or
gem5.fast? Maybe a pure python method or a C++ interface like CXXConfig ?
Thanks + regards,
Ziyang
_
Dear gem5 Community,
I hope this email finds you well. I am currently working on a project that
involves using ARM SVE in gem5 FS mode, and I have encountered a problem that I
would appreciate your help with.
While using the ARM SVE in gem5 FS mode, I added the command line parameter
"--param
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