[gem5-users] Re:CHI - data/tag latency modelling for HNF/L3$

2022-04-07 Thread zexin Fu via gem5-users
Hi, Javed I think you can add your config at CHI.py like: class HNFCache(RubyCache): dataArrayBanks = 1 dataAccessLatency = 1 tagArrayBanks = 1 tagAccessLatency = 1 size = options.l3_size assoc = options.l3_assoc Fu___ gem5-users mailing l

[gem5-users] Multi-thread simulation support in gem5

2022-04-07 Thread njuwulizhou--- via gem5-users
Hi Jason and all, We are looking for methods to speed up our gem5 simulations. One of the methods we are very interested in is multi-threaded simulation exploiting the multi-core resources in our host computers. Howerver, it seems that the current version of gem5 is basically single-threaded, n

[gem5-users] Multi-thread simulation support in gem5

2022-04-07 Thread njuwulizhou--- via gem5-users
Hi Jason and all, We are looking for methods to speed up our gem5 simulations. One of the methods we are very interested in is multi-threaded simulation exploiting the multi-core resources in our host computers. Howerver, it seems that the current version of gem5 is basically single-threaded, n

[gem5-users] Multi-thread simulation support in gem5

2022-04-07 Thread njuwulizhou--- via gem5-users
Hi Jason and all, We are looking for methods to speed up our gem5 simulations. One of the methods we are very interested in is multi-threaded simulation exploiting the multi-core resources in our host computers. Howerver, it seems that the current version of gem5 is basically single-threaded, n

[gem5-users] Multi-thread simulation support in gem5

2022-04-07 Thread njuwulizhou--- via gem5-users
Hi Jason and all, We are looking for methods to speed up our gem5 simulations. One of the methods we are very interested in is multi-threaded simulation exploiting the multi-core resources in our host computers. Howerver, it seems that the current version of gem5 is basically single-threaded, n

[gem5-users] CHI - data/tag latency modelling for HNF/L3$

2022-04-07 Thread Javed Osmany via gem5-users
Hello I am trying to model a multicore SOC system using Ruby and CHI and I am trying to model data/tag latency for the L3$ which resides in the HNF. Looking in CHI.py and CHI_config.py, I could not see any mechanisms to model this. Could someone please let me know if this is possible and if so