[gem5-users] gem5-systemc builidng error

Hi， I am a new to gem5 and want to do some research on SystemC co-simulation. I get the code from https://github.com/gem5/gem5, follow the steps the README both in /util/tlm and /util/systemc and get quite a lot building error likes xxx should be gem5::xxx or gem5::yyy should be yyy. After fix

[gem5-users] Re: gem5 : X86 + GCN3 (gfx801) + test_fwd_lrn

Matt P or Srikant: can you please help David with the latency question? You know the answers better than I do here. Matt From: David Fong Sent: Wednesday, March 16, 2022 5:47 PM To: Matt Sinclair ; gem5 users mailing list Cc: Kyle Roarty ; Poremba, Matthew Subject: RE: gem5 : X86 + GCN3 (gf

[gem5-users] How do I disable most statistics in the stats.txt under Atomic CPU

Hi All: In the Atomic CPU, only a function simulation is performed for enabling or debugging applications. The performance statistics of the architecture are not concerned. Therefore, only a small items are required, e.g. number of instructions or cycles. According to my understanding,

[gem5-users] Re: gem5 : X86 + GCN3 (gfx801) + test_fwd_lrn

Hi Matt S, Thanks again for your quick reply with useful information. I will rerun with -reg-alloc-policy=dynamic in my mini regression to see If it makes a difference As for LRN, I won't make modifications to lrn_config.dnnmark unless it's required to run additional DNN tests. The 4 tests : test

[gem5-users] Re: Gem5/DRAMSim3

Hello Kazi, Can you direct me on how I can reproduce the error you are getting? Can you please answer the following questions? - What script are you running? - What command are you using? - What version of gem5 are you using (which commit/branch)? - Did you build gem5 with DRAMSim3? Best Regards

[gem5-users] Re: Boot gets stuck sometimes ARM FS + KVM + 8 CPUs

Hi Pedro, The GIC is indeed the likely culprit as 8 PEs is the architectural limit of GICv2 (which is the interrupt controller used by VExpress_GEM5_V1, the default fs_bigLITTLE.py platform). If using KVM I honestly don’t see an easy way around it: we have on upstream a device driver modificat

[gem5-users] [Mapping 2 HW memories ranges to make them accessible by the application in SE mode]

Hi, I am building a system with two memories in SE mode. I would like to know how to map those two memories in order to make them accessible by the application ? Currently gem5 is seamlessly able to access only one of the memory since the mapping has been done. How can we add the mapping of the

[gem5-users] Boot gets stuck sometimes ARM FS + KVM + 8 CPUs

Hi all I'm trying to boot arm FS with KVM in an ARM machine (an Nvidia Jetson) with multiple cores. I had it working last year, on gem5 version 21.1.0.0. Later I had to update gem5 to version 21.1.0.2 because of some errors in the stats generation of version 21.1.0.0. So I had a lot of problems

[gem5-users] Issue with integrating DRAMSim3

Following the procedure in https://github.com/gem5/gem5/tree/stable/ext/dramsim3#readme , I integrated DRAMSim3 with the recent Gem5-stable version. But when I execute the following, ./build/X86/gem5.opt configs/example/se.py --cmd=tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TimingSim