Hello Jason:
For L0 cache in the MESI_Three_Level protocol, the cache block is initially in
the M state, I considered two ways of state transition, which one do you think
is more reasonable ？
(1) In this case, the M state of L0 is directly changed to the I state, and the
data is directly sent
Hey Krishnan,
I know very little about Ciro Santili's scripts, so I struggle to see what
you're doing. I suspect in this example you are _just_ booting the kernel
with literally nothing else (and possibly on the Atomic CPU?). This will be
faster than a complete OS boot, but I normally run on the a
One thing to try, that program looks like it needs --num-cpus=5 as it spawns 4
threads (so main + 4 total).
From: Bobby Bruce via gem5-users
Sent: Thursday, October 15, 2020 10:13 PM
To: gem5 users mailing list
Cc: Farhad Yusufali ; Bobby Bruce
Subject: [gem5-u
That's good to know, thanks, Ryan!
Is there any reason not to merge this? I know it's not a "perfect"
solution, but it would be nice if people didn't keep running into this
issue.
Bobby, can you test on both Intel and AMD (let me know if you need access
to an Intel machine). If it works, can you
Hi Bobby,
Thank you for your response. You have mentioned that linux takes longer to
boot. I just want to confirm if it is linux or ubuntu which is making the
boot time longer.
I just found a GitHub repo (
https://github.com/cirosantilli/linux-kernel-module-cheat) which uses
buildroot instead of ub
