[gem5-users] Bypassing the last level cache in the response path

Hi all, I am using classic cache models in gem5. I have three levels of caches in the hierarchy: L1-D/I, L2, L3. Whenever there is an L3 miss, the data is fetched from memory and written to L3 using a latency equals to the response latency of L3. After tracing a memory request packet, I ha

[gem5-users] Re: Few questions about cache inclusiveness

Thank you, Nikos. I will try both of them. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: How to get program specific traces only?

Hi Carlos Silva Junior: Thanks for your reply. By program specific traces/messages what I mean is, let's say I have a simple binary for "hello", is there a way I can get messages/traces that are accounted for executing this "hello" binary. The communication monitor captures any packets passed

[gem5-users] Re: How to get program specific traces only?

Hi Ahmed, I don't know what you mean by program specific traces. To get customized output from a debug-flag, I would suggest you create your own debug-flag and printing the information that you want. (http://learning.gem5.org/book/part2/debugging.html#:~:text=gem5%20provides%20support%20for%20

[gem5-users] How to get program specific traces only?

Hi all, I am using a communication monitor(CommMonitor) to observe packets exchanged at a master and slave interface using the following command: build/X86/gem5.opt --debug-flags=CommMonitor --debug-file=sum_cpu.txt.gz configs/example/se_edit.py -c tests/test-progs/hello/bin/x86/linux/main -n 1

[gem5-users] tutorials about gem5-gpu

Hi, All, I am trying to get started with gem5-gpu, are there any tutorials about it for beginners? Best regards. Shougang ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistin

[gem5-users] Re: AMD GCN3 - X86KvmCPU usage - Segfault encountered

Thanks for the heads up Matt. Virus-free. www.avast.com

[gem5-users] Re: AMD GCN3 - X86KvmCPU usage - Segfault encountered

Matt P (CC'd) will likely know better than me, but I don't believe KVM/fast-forwarding works with GCN3 yet. Matt On Mon, Sep 7, 2020 at 9:36 AM Sampad Mohapatra via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > I am using the staging branch GCN3. While using the KvmCPU to fast forward >

[gem5-users] IEEE/ACM NOCS 2020 (Sept 24-25) - Call for (virtual) participation

Dear Garnet (+ gem5) users, On behalf of the organization committee of the 14th IEEE/ACM International Symposium on Networks-on-Chip (IEEE/ACM NOCS 2020), it is my pleasure to invite you to participate in the upcoming conference, held as a global virtual event on S

[gem5-users] AMD GCN3 - X86KvmCPU usage - Segfault encountered

Hi All, I am using the staging branch GCN3. While using the KvmCPU to fast forward execution till my GPU kernel launches using m5_switch_cpu(), I am encountering a segfault at the following location: src/cpu/kvm/vm.cc:562 : long KvmVM::allocVCPUID() { return nextVCPUID++; } For some reason the m

[gem5-users] Re: Few questions about cache inclusiveness

Hi Saideepak, In the classic memory system when you configure the cache to be mostly inclusive, you always allocate on fetches and writebacks. There are a few cases where mostly-inclusive deviates from strictly-inclusive and iirc the most common one should be when a cache (e.g., LLC) evicts a li

[gem5-users] Few questions about cache inclusiveness

Hi all, I found that the classic caches in gem5 are either mostly inclusive/mostly exclusive. I need the cache to be strictly inclusive i.e if a block gets evicted from L2 that has to be evicted from L1 too. Apart from that, I have done some of my work in classic caches already. 1. Is it possib