Hi Sampad,
The AMD folks that are CC'd are better people to comment than me, but I
believe the L3 cache is a "memory side" cache, and thus doesn't need to
maintain coherence.
If you have a fix to add hits/misses for any of these files, and are
willing to contribute it back, it would be great if y
Hi Matt,
I am currently trying to add the stats by myself. I also noticed that
neither hit nor miss stats are updated for L3 Cache.
But, I am facing a different issue now. The directory ctrl (DirCntrl) in
GPU_VIPER.py has a L3 cache (L3Cache).
But, there is also a separate L3Cntrl class which inh
I've been using gem5 to analyze control algorithms performance with the
following models:
ISA: ARM
CPU Model: HPI
Memory Model: Classic
gem5 binary: gem5.fast
And I would like to extract from the stats file the RAM occupancy during loops
of program execution, but all I could find related to that
Hello,
This depends on your memory system. If your cache can accept more than one
request per cycle, then the CPU can send more than one request. The
`sendTimingReq` returns false when the receiver cannot receive another
request.
It's hard to know exactly what your memory system looks like, but i
Hi,
peak power refers to the peak dynamic + total leakage. Peak dynamic is
kinda like a TDP value, meaning that it is what a fully active circuit
would give you (let's call the scenario a power virus, not an actual
working code). When you execute a specific code on your simulator and use
the diffe
