There is no stupid question around here, ask away :-)
On Wed, May 6, 2020 at 10:33 PM Øivind Harket Bakke via gem5-users
wrote:
>
> Dear Santilli,
>
> that fixed everything except my embarrassment.
> Thank you very much, really appriciated!
>
> Best regards,
> Øivind
> ___
Dear Santilli,
that fixed everything except my embarrassment.
Thank you very much, really appriciated!
Best regards,
Øivind
___
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Maybe did you mean to use -ExecMicro to remove microops rather than
-ExecMacro? E.g. one STP generates 4 microops as shown at:
https://cirosantilli.com/linux-kernel-module-cheat/#gem5-execall-trace-format
On Wed, May 6, 2020 at 8:54 PM Øivind Harket Bakke via gem5-users
wrote:
>
> Hi all,
>
> I
Hi Jason,
I read through the documentation you linked me and I've actually looked at it
before. Only problem is that I need an in-order cpu to represent the hardware
that we use. I'll take a closer look at it and see if I can make it work, or
atleast run some tests with this to learn more about
Hi Jason,
thank you very much for your fast reply.
I thought about what you wrote and it makes sense. I thought by having only a
cpu and memory, I could remove the timing of the memory to simulate the CPU
alone. Would have been somewhat a dirty solution anyway.
Thanks again.
Best regards,
Øiv
Hi Øivind,
I would check out the documentation on the TraceCPU:
http://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU. I think
that page describes how to capture the traces.
Cheers,
Jaosn
On Wed, May 6, 2020 at 12:53 PM Øivind Harket Bakke via gem5-users <
gem5-users@gem5.org> wrote
Hi Øivind,
Atomic mode should not be used for timing. While *some* timing is required
even in atomic mode (gem5 is still an event driven simulator), the timing
is meaningless.
To answer your question as to "why": it's because only the memory system is
"atomic" the rest of the simulator is still o
Hi all,
quick question regarding atomic memory. I'm using the starter_se.py config
script (gem5/configs/example/arm/) and with memory mode being atomic. For what
I understood, using atomic memory mode should provide the data irregardless of
its position in memory(L1, L2 or off-chip mem) within
Hi all,
I'm currently trying to export traces from a simulation, but I'm only
interested in the instructions that are being simulated. I compare the stats
file (# of simulated instructions) to the traces and they don't match in size.
I've tried to figure out which are the excessive lines in ord
