[gem5-users] Simulating multiprogrammed & multithreaded workloads in SE mode?

2016-11-17 Thread Majid Namaki Shoushtari
I was wondering if there is a way to simulate multiprogrammed/multithreaded workloads in SE mode? Just to clarify: I mean running for example two programs that spawn 4 threads each. As I understand this is not possible with the current se.py script, but is it theoretically possible to run such sim

Re: [gem5-users] Understanding of cache trace of ALPHA timing CPU

2016-11-17 Thread mengyu liang
Dear all, Thanks a lot for all your explanation below. I'm now sticking to the classical Xbar memory system, not the ruby one. I accept the fact that the state transition or cache coherency takes zero time in this case. However today I studied the exec debug trace again for ALPHA FS simulation

Re: [gem5-users] Understanding of cache trace of ALPHA timing CPU

2016-11-17 Thread mengyu liang
Dear all, Thanks a lot for all your explanation below. I'm now sticking to the classical Xbar memory system, not the ruby one. I accept the fact that the state transition or cache coherency takes zero time in this case. However today I studied the exec debug trace again for ALPHA FS simulation

[gem5-users] gem5 smt in SE mode

2016-11-17 Thread Antonios Manousis
Hello, I am very new to gem5 and I am trying to experiment with different fetching policies for simultaneous multithreading. The command I run is the following build/X86/gem5.opt configs/example/se.py --ruby --cpu-type=detailed --smt -c 'tests/test-progs/hello/bin/x86/linux/hello;tests/test- prog

Re: [gem5-users] vector (NEON) instructions missing in execution trace

2016-11-17 Thread Fernando Endo
Hello, They should be implemented in gem5, but not necessarily the coprocessors that VMSR(RS) moves data from/to. The instruction definitions are in src/arch/arm/isa/insts/. You can grep there. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-11-10 16:55 GMT