[gem5-users] Error while executing gem5

Hi all, when I gave the command build/X86/gem5.opt configs/example/fs.py -b fft --ruby following errors are coming Global frequency set at 1 ticks per second warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) inf

[gem5-users] Partitioning of L2 cache based on thread requirements (Ruby)

Hi all, I am doing a project on partitioning L2 cache based on thread requirements.To assign the partition ,I need to get the ids of thread using each data block, but in gem5 number of thread per core is one. So, can anyone please tell me how the number of threads specified in the parsec be

Re: [gem5-users] How to use stack distance calculator in gem5.

Hi Andreas I want to measure the stack distance for l2 cache. So, tried to place the CommMonitor between toL2Bus.master and l2cache.cpu_side in BaseCPU.py as: #self.toL2Bus.master = self.l2cache.cpu_side #self._cached_ports = ['l2cache.mem_side'] self.l2MONITOR = CommMonitor

Re: [gem5-users] ssh to localhost in FS mode - which port should I use?

Thanks for this suggestion. I am working on X86. I think the key problem in my case is the localhost port. I can ping localhost correctly, but no port is listening. Do I need to manually open a port with iptables or other tools? On Wed, Nov 4, 2015 at 8:15 AM, Rodrigo Cataldo wrote: > Hello, >

Re: [gem5-users] InOrder ARM processor

Hello, You can use the MinorCPU model with for example: build/ARM/gem5.opt configs/example/se.py --cpu-type=minor -n 1 --caches --l2cache ... Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-11-05 12:48 GMT+01:00 Khaled Attia : > Hello, > I was wondering i

Re: [gem5-users] ARM cortex A-15 configuration

Hello, Accordingly to "Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures", Blem, E., the A15 has a ROB with 60 entries (footnote p. 8). The configurations in [1], both for the A7 and A15, were not compared to real HW. They were based on the authors kno

Re: [gem5-users] Can gem5 take instruction trace as input

Hello Pierre-Yves, Thanks, I have seen this paper, but this is not what I want. I might have not described my question clearly. What I want is still an execution-driven cycle-accurate simulator. The difference is that the input is not a full-fledged .elf binary, but some assembled machine code ins

Re: [gem5-users] CPU Configuration

Hi Arthur Perais, Thanks for your response. I have a question regarding blocking & unblocking of decode stage. Could you please help me in understanding them. I am working on a O3 CPU model with below configuration fetchToDecodeDelay = 1 fetchWidth = 8 decodeToFetchDelay=1 decodeWidth = 4 skid-b

[gem5-users] InOrder ARM processor

Hello, I was wondering if the InOrder model is currently supported for ARM architecture? If it is supported, how can I use it in my simulation script. For example, when I want to use the O3 model for ARM I use "arm_detailed" model. What should I use for InOrder ARM model (like Cortex-A8 for example

[gem5-users] To modify gem5(Ruby) for multiple thread creation

Hi all, I want to know how multiple threads are created in gem5. Default number of threads in gem5 per core is 1 .So which part of the gem5 code(RUBY) should be modified to generate multiple threads.Also ,how the number of threads specified in the Parsec benchmark script get assigned to the

Re: [gem5-users] Gem5 and SystemC

I'll take a look, thank you. On 05/11/2015 10:23, Andreas Hansson wrote: > Have you tried using: http://reviews.gem5.org/r/3132/ ? > > Andreas > > On 05/11/2015, 09:09, "gem5-users on behalf of Pierre-Yves Péneau" > > wrote: > >> Hi, >> >> Thank you Andreas for your quick response. >> >> When

Re: [gem5-users] Gem5 and SystemC

Have you tried using: http://reviews.gem5.org/r/3132/ ? Andreas On 05/11/2015, 09:09, "gem5-users on behalf of Pierre-Yves Péneau" wrote: >Hi, > >Thank you Andreas for your quick response. > >When I am using the simple example with TLM in FS mode, there is no >stats.txt and the end. I need that

Re: [gem5-users] Gem5 and SystemC

Hi, Thank you Andreas for your quick response. When I am using the simple example with TLM in FS mode, there is no stats.txt and the end. I need that file for other works, that's why I want to use Gem5 as the master and SystemC as the slave. May be am I missing something ? Thanks. On 05/11/2015

Re: [gem5-users] Gem5 and SystemC

Hi, gem5’s event model is a subset of SystemCs, so wrapping SystemC in gem5 will be challenging. In essence gem5 only supports SC_METHOD style concurrency, and we would need some additional support in gem5 to be able to handle SC_THREAD and SC_CTHREAD. It’s not impossible, but it would be painful

[gem5-users] Gem5 and SystemC

Hi, I am looking for a solution to connect Gem5 and SystemC. I read the documentation and I tried the solution provided in the util/tlm directory. This solution is working but it's not what I want to do. In this model, Gem5 is executed as a SystemC module, so SystemC is the execution leader. I wan

Re: [gem5-users] Can gem5 take instruction trace as input

Hi, Butko et al. have developed a trace-driven approach based on a gem5 simulation. You can find more information here [1]. Best regards, [1] http://www.lirmm.fr/~butko/files/trace-driven.pdf On 05/11/2015 01:06, Lingxiao Jia wrote: > Can someone help? If gem5 is not possible, does anyone know

Re: [gem5-users] How to use stack distance calculator in gem5.

Hi Bhaskar, Have a look at tests/config/tgen-simple-mem.py. The comm monitor has a master and a slave port, and you need to connect it “between” two other modules. There are plenty examples on the mailing list for adding it between the L1 and L2, for example by changing BaseCpu.py (if you do,