Re: [gem5-users] aarch64 (armv8-a) - question on adding a new processor support

Hi Fernando, Thanks for the information. -- with regards, Virendra Kumar Pathak ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] LSQ bottleneck when using X86 TSO

Hi Steve Reinhardt, I am working on extending store functional unit to "store-address" + "store-data" in gem5 for aarch64 arm processor. Looks like you had proposed a patch with similar aim (issue excl. prefetch as soon as store address is available) Mailing archive link - https://www.mail-archi

Re: [gem5-users] ARM cortex A-15 configuration

Hi, Thank you for your fine grained tests, I will change my configuration right now. Best regards. On 01/11/2015 20:37, Prathap Kolakkampadath wrote: > Hello Pierre/Fernando, > > > Thanks for your replies. > Based on [1] the ROB entries for cortex-A15 is 60. However, as per this > article > ht

Re: [gem5-users] How to use stack distance calculator in gem5.

Hi Bhaskar, There are a few steps you need to take, and it involves a few widely-adopted gem5 concepts: - First, the stack distance calculator is a probe, and the output is in the shape of gem5 stats. Thus, you need to instantiate the probe, and attach it to a probe point. - Second, to be abl

[gem5-users] communication between TLB and SLICC

Hi All, I am modifying the changes in TLB.cc .I think it is cache independent . Is there any way to communicate the TLB.cc and L1cche controller for any coherence protocol. Or solution is Write the code of TLB behaviour on SLICC . How do i do that? Please guide me regarding this. -- Bha