Hi Anderson,
Thanks for the reply, however I still face the problem.
Following is the new script.
--
#import m5
#from m5.objects import *
import m5
from m5.objects import *
MyCache=BaseCache(assoc=2, mshrs = 10, tgts_per_mshr=5, hit_latency=1,
response_l
Hi all,
I am new to Gem5. I need to add a new Instruction to read L2 cache
directly, while normal load/store instructions still access L1 cache first.
Does anyone know how to achieve it?
I think I need to modify part of the source code, but I have no idea how
much I should modify. I appreciate if
Hello,
If you want to run PARSEC 3.0, you need to crosscompile it for the ISA you
want, on your host (GCC crosscompilers are available at gem5 wiki, on
Download section). After that, copy the binaries and inputs to the image.
If PARSEC 2.1 is enough, you should take a look at
http://www.cs.utexas
Hi, all.
Referring to the
website http://parsec.cs.princeton.edu/parsec3-doc.htm#start
I've downloaded PARSEC 3.0 on my real machine, X86.
Except one of them doesn't work the other work fine.
Now I want to run them within GEM5 in FS mode, but the files included in
the PARSEC suite
seem too
Hi Hamid
can you give some further info about you work such as your commands in terminal
and gem5 configures and try on which workload of Parsec...
tell me whether the program goes ahead and in ROI stops for long time? or your
simulation endedwithout interesting result?
---
Hi all,
I am posting as a follow up of this thread
(http://www.mail-archive.com/gem5-users%40gem5.org/msg10489.html). I was having
a bad page error when running X86 FS with more than one O3 cpu. I switched to
Ruby memory model (with MOESI_hammer protocol), successfully created a
checkpoint and
Hi Naveed,
The Bus is renamed Xbar, and you need to specify either a coherent or non
coherent one. In your case:
membus = CoherentXBar()
...should do the trick.
Concerning the power and clock domains, I suggest having a look at
configs/examples/se.py and fs.py to see how it is done. If you do n
Hi All,
I am a new user of gem5. I am following the slides available on following
link.
I am running following configuration script. Lines whic prodcue error are
marked by comments
import m5
from m5.objects import *
MyCache=BaseCache(asso
Hi Andreas,
Thanks for the quick response. Yes. I could locate the memcpy in the
packet.cc/.hh file. Thanks for the response.
BR/Nizam
On Tue, Sep 30, 2014 at 7:35 PM, Andreas Hansson
wrote:
> Hi Nizam,
>
> The gem5 memory system shuffles actual data around in the packets. Just
> grep memcp
Hi Nizam,
The gem5 memory system shuffles actual data around in the packets. Just grep
memcpy in src/mem :-)
Andreas
From: Nizamudheen Ahmed via gem5-users
mailto:gem5-users@gem5.org>>
Reply-To: Nizamudheen Ahmed
mailto:nizam.ah...@gmail.com>>, gem5 users mailing list
mailto:gem5-users@gem5.
Hi champs,
I am using classic memory model for my experiments. i have a question in
this implementation of classic memory model.
Is classic memory model a dataless model? Essentially, does the Packet that
pass trough the cache model carry the data along? I could not locate code
that copies data
Hi Lokesh,
There are two key components in gem5 designed to change the frequency and
voltages dynamically:
- First, you have the DVFSHandler which is just a form of API for doing
these kinds of changes
- Second, you have an EnergyCtrl instance which is a memory-mapped
component, visible to the O
12 matches
Mail list logo
