Hi all
I am trying to share the load store queue across CPUs in gem5.
Since loadStoreQueue is an object in IEW stage, I'm not sure how it can be
shared across CPUs.
I would like to know if there is a way to do this.
Thanks a lot in advance.
V Vanchinathan
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Hi ,For the second issue, After drain, I am simply checking if all the
instructions in InstToExecute list is squashed and if they are, I am clearing
the list. If not I am exiting simulation. (Since cpu is drained and InstList is
empty, all entries in InstToExecute list must be squashed).
For
Hell All
How can I pass the tick number when ROI of a benchmark start simulating to
a function inside the cache_impl.hh ??
Thanks for your help
Hamid
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"--trace-start" and "--trace-file" were renamed to "--debug-start" and
"--debug-file"
Hope that helps.
On Tue, Apr 15, 2014 at 2:40 PM, Kuk-Hwan Kim wrote:
>
> Dear Gem5 community member,
>
> I wish to display pipeline stages from 200cycles to 1000. So, I would like
> to create trace.out by us
In O3, numCycles includes idleCycles. So busy cycles is numCycles -
idleCycles.
As a side note, there is also quiesceCycles.
Thanks,
Amin
On Tue, Apr 15, 2014 at 2:45 PM, Tiago Mück wrote:
> Hi Lluíz,
>
> I've noticed that you are using this mapping in your core template:
>
>
>
>
Dear Gem5 Community members,
I am running one of asimbench program (360buy.rcS) by using following
command-line command.
command line: ./build/ARM/gem5.opt ./configs/example/fs.py
--kernel=../../asimbench/asimbench_android_arm_kernel
/vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=../../as
Dear Gem5 community member,
I wish to display pipeline stages from 200cycles to 1000. So, I would like
to create trace.out by using following command-line command. However, I
received "no such option" error. Is the O3 pipeline viewer deprecated now?
Any help or comments are greatly appreciated.
Hi Lluíz,
I've noticed that you are using this mapping in your core template:
I think *core.numCycles* accounts only for busy cycles, so the correct
would be:
Please let me know if I'm wrong.
Also, why are you using *core.iew.iewIdleCycle* instead o
Thanks for the reply.
Regardless DVFS, if I can put the core in sleep mode, so that will affect
the accesses amount to units and the number of the busy cycles, and that
will results in less power in McPat.
So, could you please tell me if there is a way, to put some cores in a
sleep or idle mode ?
Hi Heba,
While gem5 supports DVFS (and there are more patches coming shortly), McPat 0.8
(the one that is in ext/mcpat) does not. Thus, even if a core is not doing
much, you will not see any dramatic improvements.
Andreas
From: Heba Khdr mailto:eng.k...@gmail.com>>
Reply-To: gem5 users mailing
Dear all,
I run 4 cores (full system mode) on Gem5, and run one application (x264),
with one thread only.
So, I got one core with higher dynamic power than the others, using McPat.
However the difference is not high, so that means the other core is still
running some threads from the OS kernels.
Sobhan Niknam writes:
> Hi,
> I need to use GEM5 and McPAT together. Also, I use ALPHA Architectures over
> GEM5. I need to have the power analysis of all components in Gem5 simulation.
> for extracting power from output of Gem5 with McPAT, I searched a lot, and
> find
> valid parsers or methods
Nice discussion! thanks!
Regards,
--
Fernando A. Endo, PhD student and researcher
Université de Grenoble, UJF
France
2014-04-11 18:28 GMT+02:00 Ali Saidi :
> Yes, if you have a spin lock in some code, it's highly likely that a
> faster core will spin for more instructions on that lock and t
Hi,
I need to use GEM5 and McPAT together. Also, I use ALPHA Architectures over
GEM5. I need to have the power analysis of all components in Gem5 simulation.
for extracting power from output of Gem5 with McPAT, I searched a lot, and find
valid parsers or methods to integrate GEM5 with McPAT,
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