Hi all,
Is there anyone who has an up to date gem5-to-McPat parser to generate the
input xml files for McPat?? All I found were very old ones which keep
giving errors including the ones below:
https://bitbucket.org/rickshin/m5-mcpat-parser
https://www.cl.cam.ac.uk/~acr31/sicsa/
I am using gem5 stab
The IEW statistics based on instruction class for the o3 CPU might
provide what you want. If you want to print OpClass information out in
the simple CPU it should be doable.
Ali
On 26.07.2013 17:36, Mahshid
Sedghi wrote:
> Hi,
>
> I need to find out the instruction mix for
some benchmark
gem5 doesn't currently support this, but it should be rather easy to
add.
Ali
On 29.07.2013 06:48, Sophiane SENNI wrote:
> Hi
everybody,
>
> Does someone know how can I set write latency different
from read latency for both cache and main memory ?
>
> Thank you very
much.
>
> Sophian
Just as previously posted, this is likely masking the issue, not
solving it. I don't see a reason why the application would be generating
an address that large. Either a instruction isn't being simulated
correctly or a syscall is incorrect. In short it's a bug in the
simulator and you're just ig
You've likely found a bug. SMT support in the O3 cpu isn't
frequently used, so it's very possible some bugs have crept in that
code.
Ali
On 24.07.2013 09:23, Jordan Dean wrote:
> I understand
what you mean, but my problem is a bit different. When I pass 2 programs
to a processor in SE mode
Hi,
Some architectures do support a other-endian mode (e.g. ARM
supports BE loads). I don't know that anything has been done to prevent
this from working, but similarly nothing has been done to enable it.
Assuming you can compile a program like hello world in this mode you
coun try it and see.
Hi All,
I am running the simple network, use the the command :
./build/ARM/gem5.opt configs/example/ruby_random_test.py --num-cpus=16
--num-dirs=16 --topology=Mesh --mesh-rows=4
But there is an error:
File "configs/example/ruby_random_test.py", line 153, in
exit_event =m5.simulate(options.max
Hi Yuhang,
There is no way to identify the directions of the ports since the current setup
allows you to potentially declare any topology, not just a mesh.
The way I typically do this is the following:
In GarnetNetwork_d.cc, when the router ports are being added (makeInternalLink
etc), you can se
Make sure you disable all listeners (or at least remote gdb). I would
guess someone inadvertently attached to your simulation.
Andreas
On 30/07/2013 17:16, "Jack Wu" wrote:
>Hi All,
>
>I am running some benchmarks in SE mode but for some of the benchmarks I
>am getting the following error from
Hi All,
I am running some benchmarks in SE mode but for some of the benchmarks I am
getting the following error from the terminal:
-
panic: Remote gdb clearSingleStep not implemented in x86!
@ cycle 793473930
[clearSingleStep:build/X86/arch/x86/remote_gdb.cc, line 76]
Memory Usa
Hello all,
I was wondering is that possible to implement odd even turn model in
garnet network? The router id is accessible which can determine the odd
and even column. But I cannot find a clear distribution of input/output
ports and the links to the five ports (west, east, north, south, core)
Hi,
I guess O3 doesn't model every piece of real hardware behavior at all. In terms
of squashing, squashed instruction doesn't release all resources, instead it
(squashed one) retires from ROB when it comes to ROB head.
Code handling branch miss prediction spreads around multiple files, at leas
Dear Mahshid,
Thanks for your replies. I have another question. What coherence protocol do
you use? Is it still MOESI_hammer? Moreover, could you please show me the
command you use to switch from timing to O3 CPU, right after the checkpoint is
restored?
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