Hi Chao,
I think you still have to connect the cpu ports to the l2bus. Just make
sure the options.l2cache exists, in order to make the
system.cpu[i].connectAllPorts(system.tol2bus, system.membus) works.
Best,
On Thu, Jul 18, 2013 at 10:21 AM, Chao Zhang wrote:
> Dear Trophy,
>
> Thank you
Dear Trophy,
Thank you very much!
I'm so stupid to forget the l2option issue, to connect the cpu ports to l4bus
at the end of the configuration, just as that you pointed out.
But after this has been figured out, a new error comes.
I need a cache system with shared L2, shared l3 and shared l4. So
By the way, in the inst_queue file, there's another scoreboard (
RegScoreboard ) to be used in the addtodependent part, so why wont we use
the scoreboard like we use in rename/iew stage? Does this scoreboard(
RegScoreboard) have special meaning? Or just for simplify ?
Thanks
Xiangyang
On Wed, J
Hi,
I modify the scoreboard.cc to make another scoreboard ( it is simply
another vector like the original one but contains different info) to
maintain the information if one reg is used now. It works like this: at the
dispatch stage, after one inst is dispatched successfully, then mark all
its reg
It's interesting to see following setting in config.ini file.
Why there are 2 delay defined between decode and fetch stage?
[system.cpu]
type=DerivO3CPU
decodeToFetchDelay=1
fetchToDecodeDelay=3
.
.
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Thanks for answering so quickly.
I am currently running the debug like you suggested but it is taking a
while. I wont know for some time, but the other reason it was not making sense
is that it will not run in detailed mode when i run both benchmarks, so i
cannot get IPC or any other info
Thanks for answering so quickly.
I am currently running the debug like you suggested but it is taking a
while. I wont know for some time, but the other reason it was not making sense
is that it will not run in detailed mode when i run both benchmarks, so i
cannot get IPC or any other info
Ankita, did you ever solve or work-around this panic?
On Thu, Feb 23, 2012 at 12:00 AM, Ankita (Garg) Goel
wrote:
> When I try to boot with multiple cores, I get the following error :
>
>
> warn: Address 0xffc0 is outside of physical memory, stopping fetch
> warn: Address 0xffc0 is o
Thanks a lot Amin. Now it's working. I actually had to insert the line in
Simulation.py rather than fs.py, since I switch cpus after restoring from
checkpoint and therefore, I had to assign the robsize to "switch_cpus"
rather than "system.cpu".
Appreciate your help,
Mahshid
On Wed, Jul 17, 2013
Also, if you want to make sure this is what happens, you can specify
"--debug-flag=Exec" before se.py to see the flow of instructions and you should
be able to see two different cpu in the output debug file. Then you can compare
this against running each benchmark alone on one core and see if th
Hi Jordan,
I believe the se.py script is already setup such that the first program runs on
the first core while the second program run on the second core. Someone please
correct me if I'm wrong!!
If you look at se.py:
for i in xrange(np):
if options.smt:
system.cpu[i].workload = mu
Hello,
I have been in a research program for a few weeks, and am so close to
making a real breakthrough in my topic but ran into a few major issues. They
seemed simple at first. Here is what command I am running, most of it is just
the defaults but just to show it all stays constant when i
Le 17/07/2013 17:01, Jianghao a écrit :
Thanks for your clarification. So even all resource like operands/FUs
are available, the instruction still need to wait issueLat cycles
before execution, correct?
Well it's more like the FU does not become available until issueLat cycles.
Is there a
Hi Fulya,
The m5-mcpat.pl and mcpat-template.xml on the website
https://www.cl.cam.ac.uk/~acr31/sicsa/ work for me with some modification.
1. First, you should make sure the all the value field in the
mcpat-template.xml can be found in the stats.txt or config.ini files.
Otherwise, modify them ac
On 7/17/2013 7:44 AM, Arthur Perais wrote:
My understanding is that issueLat is the minimum number of cycles you
have to wait before scheduling an instruction of the same type on the
FU. Specifically, if opLat is 6 and issueLat is 1, you have a
pipelined unit with a latency of 6 cycles but you
Hi all,
I'm planning to start using SLICC infrastructure that gem5 provides. I'm very
new to the whole Ruby system though!
Can anyone please answer these questions:
1.How do I generate c++ classes in MI_example?
2.Do I necessarily need to build a gem5 + Ruby Memory System to realize a
HI Chao,
Do you notice that there is :
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
in the original configuration file.
So, if you config l4cache, there will be no opti
Dear all,
I'm using gem5 to simulate 4 level caches under full system in gem5. But I
faced an error when set up the system.
It seams something is wrong in configurations. (I thought the error I sent to
this mail list is nothing to do with the linux kernel. XD)
So I want somebody could help me 1
My understanding is that issueLat is the minimum number of cycles you
have to wait before scheduling an instruction of the same type on the
FU. Specifically, if opLat is 6 and issueLat is 1, you have a pipelined
unit with a latency of 6 cycles but you have a throughput of 1 op/cycle
once the pi
Hi all,
I'm implement a 4-cores processing system using ARM. But the communication
between these cores should based on photonic. I cannot fiind any source
code about the photonic network modules. Could you give me some advices?
Many thanks,
Christina
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