Re: [gem5-users] Micro-TLB in Gem5 ARM model

Hi, To my understanding, separate instruction and data microTLBs are implemented in arm model with 64 entries in default. But the shared MacroTLB is missing. Best regards, Yongbing Huang From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Ami

Re: [gem5-users] Network latency breakdown for Garnet

That breakdown is not tracked. You will have to add your own counters. - Tushar Mahshid Sedghi wrote: >Hi all, > >I am using Garnet and would like to know the breakdown of the network >latency. To be more exact, I want to know the queuing latency as well >as >transfer latency. It seems that th

[gem5-users] Micro-TLB in Gem5 ARM model

Hi, I would like to know if the Micro-TLB feature is being implemented in Gem5 ARM model ? If yes, then are there separate Instruction and Data MicroTLBs ? Thanks & Regards, Amit Tara ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cg

Re: [gem5-users] gem5 stops making progress in some applications

Very strange... if it's not making progress, it must be livelocked, because otherwise you would hit the max_tick event and exit. You should be able to jump in with gdb, turn on a few trace flags, and see what's happening. If any of these are benchmarks that used to complete, you could use 'hg bis

[gem5-users] gem5 stops making progress in some applications

Hi Everyone, Has anyone else noticed odd behaviour where gem5 stops making progress in some applications? I'm currently experiencing this on an x86 system simulating an x86 system in FS mode. I've seen this happening in some of the SPEC CPU2006 benchmarks (450.soplex/ref, 454.calculix/ref, 4

Re: [gem5-users] Obtain cache miss penalty cycles

You should look at handleResponse function in cache_impl.hh. Based on the type of the request type (read or write), you could get the penalty. On Thu, Jul 4, 2013 at 3:48 PM, Bhawna Jain wrote: > How can we obtain cache miss read and write penalties in gem5? Not average > but exact miss penalty

[gem5-users] Obtain cache miss penalty cycles

How can we obtain cache miss read and write penalties in gem5? Not average but exact miss penalty for a single read and single write. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users