Thanks Andreas,
I could get a unique masterID from the system by providing a string.
-Uday
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Andreas Hansson
Sent: Monday, June 24, 2013 5:28 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] masterID for s
If you are working on cache mgmt policies, then improvement in the
execution time is the right metric and not the ipc.
On Tue, Jun 25, 2013 at 6:13 AM, Rodrigo Reynolds Ramírez <
rodrigo.r...@hotmail.com> wrote:
> Thanks Joel, I looked that for comparing the use of each cpu, it seems ok.
> Becau
Thanks Joel, I looked that for comparing the use of each cpu, it seems ok.
Because I am working with cache policies I also need the ipc as a performance
metric, now I know that the ipc I am getting are ok. Thanks again
Rodrigo
Date: Mon, 24 Jun 2013 14:21:57 -0500
From: jthestn...@gmail.com
To:
Do we have any control on how a masterID is assigned? I mean, how can I
make sure a specific core always gets a pre-defined master ID?
Thanks,
Amin
On Mon, Jun 24, 2013 at 4:58 AM, Andreas Hansson wrote:
> Hi Uday,
>
> Sure. In that case I'd say add another unique value and (re)use that for
>
I have a questions about ARM ISA implementation.
From the document, instruction "format" is basically a Python function
to generate up to four pieces of C++ code.
If it's nested format structure like following code, which one will be
used, DataOp, ArmMultAndMultAcc or both for the multiply instr
Hi all
I am a gem5 newbie. My aim is to simulate a asymmmetric
multicore(num-cpus=2) i.e one inorder and other out of order on ARM
platform and I am using the se.py configuration script. I have added an
extra option to take two cpu classes and have modified the CpuConfig.py,
Simulation.py to accom
Hi Rodrigo,
It is likely that instructions involved with synchronization will affect
the absolute instruction counts on cores that wait for other cores (and
thus, the IPC). A better metric for analyzing the balance of work between
cores is the mix of instructions that they commit (e.g. integer,
Yes, I runned it for the ROI from a checkpoint, I got three sets of statics, I
copy the results for ROI.
Rodrigo
Date: Mon, 24 Jun 2013 21:44:30 +0530
From: biswa@gmail.com
To: gem5-users@gem5.org
Subject: Re: [gem5-users] Parsec and Alpha
No that's not the case always. Did you run for the R
No that's not the case always. Did you run for the ROI?
On Mon, Jun 24, 2013 at 9:35 PM, Rodrigo Reynolds Ramírez <
rodrigo.r...@hotmail.com> wrote:
> I think the OS scheduler tries to balance the cpu's load avoiding that ipc
> difference.
>
> Rodrigo
>
> --
> Date: M
I think the OS scheduler tries to balance the cpu's load avoiding that ipc
difference.
Rodrigo
Date: Mon, 24 Jun 2013 19:48:55 +0530
From: biswa@gmail.com
To: gem5-users@gem5.org
Subject: Re: [gem5-users] Parsec and Alpha
why would the ipc be same?
On Mon, Jun 24, 2013 at 7:33 PM, Rodrigo
why would the ipc be same?
On Mon, Jun 24, 2013 at 7:33 PM, Rodrigo Reynolds Ramírez <
rodrigo.r...@hotmail.com> wrote:
> Hello everyone
>
> I am currently working with parsec+alpha, I have executed some tests using
> the small inputs using two cpus, is it normal to get a very unbalanced ipc?
>
Thanks so much, Andreas. - 원본 메일 -보낸사람: Andreas Hansson 받는사람 : gem5 users mailing list 날짜: 2013년 6월 24일 월요일, 01시 50분 52초 +0900제목: Re: [gem5-users] Disk image with COW layer on Gem5: How to make asimulation realistic?
Hi Tod,
Great care has been taken to mak
Hello everyone
I am currently working with parsec+alpha, I have executed some tests using the
small inputs using two cpus, is it normal to get a very unbalanced ipc? These
are my results:
Bench / IPC
CPU0
Hi Uday,
Sure. In that case I'd say add another unique value and (re)use that for all
these requests. You can simply ask the system for one on initialisation. There
is no functional need for the masterID. It's only used for the book keeping.
Andreas
From: , L Udaya mailto:udayara...@ti.com>>
R
Hi Andreas,
What you say is true for an interconnect-like module that uses a "normal"
request to create a "snoop" request.
But, in my case, I have to create a snoop request from scratch because this
snoop request originally is from an interconnect-like module in a different bus
protocol domain
Hi Uday,
If you need to send requests I would imagine you want a master port. A snoop
request would typically be created from a "normal" request and thus copy its
master id.
Andreas
From: , L Udaya mailto:udayara...@ti.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date:
Hi,
I have a module (derived from SimpleMemory) which has an instance of type
'SlavePort'. I need to call sendTimingSnoopReq( PacketPtr ) on this port. For
this I have to first create a Request and then Packet.
Request() constructor needs a mastered. I understand that typically this is
obtaine
Hello,
I think it depends on what memory model one is simulating. If you're using
the classic model, than number 2 may define the cache latency.
You can change them, run and see if the config.ini will reflect the changes.
Regards,
--
Fernando A. Endo, PhD student and researcher
Université de G
Hello,
Regarding the McPAT error, I suggest putting a breakpoint where the error
is generated and backtracing to find which parameter in the XML is causing
this problem.
Hope it helps,
--
Fernando A. Endo, PhD student and researcher
Université de Grenoble, UJF
France
2013/6/19 Yuhang
> Hel
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