[gem5-users] Cache Miss Rate Calculation

2013-06-11 Thread Mahshid Sedghi
Hi all, I'm trying to calculate L1 and L2 cache miss rates for a full system simulation using ruby (MESI_CMP_directory) + garnet. I dump stats periodically to get the trend of the rates. I can see that in ruby.stats, total_misses for each L1 and L2 cache bank is reported. Also, I can see the even

[gem5-users] Thread switch

2013-06-11 Thread Yanqi Zhou
Hey everyone, Do anyone know how to force a thread switch when running multithreaded benchmark, such as PARSEC? I am not a good hacker, and cannot figure out a way... I appreciate any suggestion. Yanqi ___ gem5-users mailing list gem5-users@gem5.org htt

Re: [gem5-users] buffers in the router

2013-06-11 Thread Tushar Krishna
The organization is as follows: Each Input Unit has a vector of Virtual Channels Each Virtual Channel has a member called flitBuffer_d Each flitBuffer_d is a vector of flits (flit_d) Each flit_d carries a actual message (MsrPtr) in addition to network related information (route, vc id etc etc). If

[gem5-users] buffers in the router

2013-06-11 Thread amina belhaj messaoud
Hello every body , How can I access to the buffers of the virtual channel allocator of the garnet (fixed pipline )router in order to insert a bit flip in it , in fact I found the class of the vcallocator , but the flit_buffers are not memory objects so that I can acess there adress range , It wil

Re: [gem5-users] MessageBuffer Usage

2013-06-11 Thread Mann
Thanks a lot Tushar It gave a direction to begin with, and what options are doable. cheers.. Mann ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] cpu registers value

2013-06-11 Thread Fernando Endo
Hi Ali, The files regarding the O3 model are here: src/cpu/o3/ Not sure if the best place is the following, but the register file is accessed in the iew stage. Hope it helps, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2013/6/8 ali bagherian > Hi Fern

Re: [gem5-users] ARM InOrder implement

2013-06-11 Thread Korey Sewell
McPAT is only generating power #s for resources that you tell it to generate power for. So even if you simulate it with a stripped down O3 (mimicking InOrder), you only have to give McPAT cycle+activity counts for resources that you need power for. -Korey On Sat, Jun 8, 2013 at 10:34 AM, Xiangy

Re: [gem5-users] LibPython Problem

2013-06-11 Thread Erfan Azarkhish
D ear Ali, I installed this library: libssl0.9.8, and then ran the build again, but nothing changed. The strange thing is that, when I use the following command for build everything is ok: *scons build/ALPHA/gem5.opt* but when I use this one, I see the link errors: *scons build/ALPHA_MOESI_hammer