Hi, All.
I was wondering if anyone can make a quick check for L2cache misses in ruby.
It seems like the number of L2cache access and miss doesn't show proper
numbers.
In my simulation, L2cache miss is the exactly same number of L1Dcache miss
+ L2Icache miss...
For example...
L1 Dcache Access 110,7
Hey guys,
I'm wondering if it's possible to pass parameters to the Linux kernel in
full-system mode. If so, can you point me to how to do this?
Background: I've narrowed the x86 full-system IDE bug down to some
incorrect handling of IDE channels in Linux, and I may have uncovered a fix
(here:
Hi all,
As some of you may have seen, we propose making gcc 4.4 or clang 2.9 the
minimum compiler requirements: http://reviews.gem5.org/r/1556/. See the patch
for more details about the why, what and how.
Should there be anyone that feels very strongly about this, please let me know,
preferabl
Hi all,
I am dumping stats (in the ROI of canneal benchmark)
periodically. I have observed that the total number of instructions , sim_insts,
across all cores and for all periods is much larger than the total number of
instructions inside ROI and without period dumping, however the total number
Hi Abhiskek,
You do not need to worry about changing any coherent protocol, just place an L3
cache in the right spot. The code you have inlined looks suspicious.
I'd say something like:
system.l3cache = L3Cache(…)
system.membus.master = system.l3cache.cpu_side
system.l3cache.mem_side = system.p
On Fri, Dec 7, 2012 at 7:44 AM, Nilay Vaish wrote:
> On Thu, 6 Dec 2012, Abhishek Deshpande wrote:
>
> Hi,
>> I am new to Gem5.
>> Please let me know how to enable L3 and confirm that it is working. I am
>> using ALPHA architecture available in gem5 without any modification and
>> using se.py co
On Fri, 7 Dec 2012, Anouk wrote:
Hi Nilay,
Thanks for your answer.
I am changing my response. Depending on the protocol, there are operations
that are carried out which might be termed as re-ordering. For example, a
controller may block all messages while it is waiting for a particular
me
Hi Nilay,
Thanks for your answer.
Kind regards,
Anouk
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On Fri, 7 Dec 2012, Anouk wrote:
Hi,
I have a question regarding message ordering in Ruby.
Because the SimpleNetwork offers adaptive routing, in which messages can proceed
in the network out-of-order, I always assumed some kind of re-ordering was in
place.However, I made some changes to the net
On Thu, 6 Dec 2012, Abhishek Deshpande wrote:
Hi,
I am new to Gem5.
Please let me know how to enable L3 and confirm that it is working. I am
using ALPHA architecture available in gem5 without any modification and
using se.py configuration file as available.
Since you have not made any changes
Hi,
I have a question regarding message ordering in Ruby.
Because the SimpleNetwork offers adaptive routing, in which messages can proceed
in the network out-of-order, I always assumed some kind of re-ordering was in
place.However, I made some changes to the network which makes it possible for
mes
Hi all,
For present,does splash can be run in SE mode?
Under SE mode, I run FFT from splash2 on 64-CPUs, and I find that the
utilization rate of CPU0 is about 80%, however, the utilization rate of other
CPUs are much small, e.g. below 10%. I wonder the reason and how to fix it.
Regards.
John
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