Hi,
I tried printing the number of input ports and output ports from
SWallocator.cc using this
*m_num_inports = m_router->get_num_inports(); //return
m_input_unit.size()*
*m_num_outports = m_router->get_num_outports(); *
It prints the values as 4 input ports and 4 output ports. I had read
so
Hi Tushar,
I had resumed working on this again, so was going through your
emails(please see email below). I am still getting this error:
gem5.debug: build/ALPHA_SE_MOESI_hammer/base/cast.hh:49: T safe_cast(U)
[with T = const MemoryMsg*, U = Message*]: Assertion `ret' failed.
Program aborted at cy
Yes 1-flit packets (of type HEAD_TAIL_) are control messages from the protocol.
- Tushar
On Sep 25, 2012, at 8:04 PM, Pavan Poluri wrote:
> Hello,
>
> I have a question on the single flit packets generated when synthetic traffic
> simulation is used. These 1 flit packets are of type HEAD_TAIL
Hi Nilay,
Sorry that I forgot to ask a question. I have tried to use the default
clock rate for cpus (2GHz) and it boots successfully. I wonder if it is
possible to have cpus with 5GHz clock rates. If so, what's the correct way
to make it work. Is there a limit for the maximum clock rate in X86
Hi guys,
I want to boot more than 256 cores in X86 FS with ruby, however, it's slow.
More than 3 hours for ~60 cores so far without ruby...
I read this from X86 session of http://gem5.org/Architecture_Support :
"patches are available for speeding up boot"
I have searched around, but couldn't fi
Thanks Nilay!
Best,
Jun
On Tue, Sep 18, 2012 at 11:58 PM, Nilay Vaish wrote:
> You might want to try with a different setting for the clock parameter.
>
> --
> Nilay
>
>
> On Tue, 18 Sep 2012, Jun Pang wrote:
>
> Actually, it also happens to multiple cores without ruby.
>>
>> Does anyone know
Hello,
I have a question on the single flit packets generated when synthetic
traffic simulation is used. These 1 flit packets are of type HEAD_TAIL_.
According to the default settings, control message (8 bytes) occupies 1
flit and a data message (72 bytes) occupies 5 flits, where each flit is 16
b
Please anyone
can explain about Codebench Courcery installtion and use with gem5 and
benchmarks.
I want to use it for ARM processor. I am at Ubuntu 12.04 desktop workstation
8.0 VM. After testing will explain here please.
regards
Musharaf
___
Never mind. I figured it out. Looks like the default scons on my system was
somehow "hard" combined with python 2.6. I downloaded scons-local, and used
"python scons.py build/X86/gem5.opt" to compile gem5. The problem is gone,
and gem5 runs fine.
Lide
On Tue, Sep 25, 2012 at 1:26 PM, Lide Duan w
Hi,
I was able to compile gem5 (X86), but when running it, it always complains:
sc2b0646[68]% ./build/X86/gem5.opt
Traceback (most recent call last):
File "", line 1, in
File
"/proj/bobcata_perf_user3/duan/gem5/gem5-stable/src/python/importer.py",
line 73, in load_module
exec code in mod
Hello
Pavlos Maniotis.
You try to understand about gem5 a little bit and keep with gem5 mailing list
please.
thanks
Musharaf
--- On Tue, 9/25/12, Pavlos Maniotis wrote:
From: Pavlos Maniotis
Subject: Re: [gem5-users] question about cache memory and gem5
To: "gem5 users mailing list"
Date
Hello Musharaf Hussain,
Thank you for the reply. I have already started working
on this. I managed to compile gem5 and I have simulated
the X86 architecture by running some custom code!
I am studying the material on the website and after
understanding more about the simulator I aim to simulate
a
Hi, Maniotis Pavlos.
You can do with gem5. At first you should try and see the tutorials and slides.
musharaf
--- On Mon, 9/24/12, Pavlos Maniotis wrote:
From: Pavlos Maniotis
Subject: [gem5-users] question about cache memory and gem5
To: gem5-users@gem5.org
Date: Monday, September 24, 2012
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