Re: [gem5-users] Set total order among multiple logic buses

Thanks Tushar! Jinzhu On Tue, Aug 28, 2012 at 3:15 PM, Tushar Krishna wrote: > Hmmm the ruby_network_tester is supposed to be used only with the > NetworkTest coherence protocol … > Not sure how it interacts with other protocols. > With Hammer, I would suggest using ruby_random_test > > Don't k

Re: [gem5-users] Checkpointing possible with Ruby, X86, TimingSimpleCPU and O3CPU?

The cause of the assert failure was tracked down recently by Jason Power. The patch is on the review board. Here is the link - http://reviews.gem5.org/r/1365 It will be committed to the mainline soon. -- Nilay On Tue, 28 Aug 2012, Marco Elver wrote: Hi all, I would like to ask if what I a

[gem5-users] Checkpointing possible with Ruby, X86, TimingSimpleCPU and O3CPU?

Hi all, I would like to ask if what I am trying to do is even possible (and if so, how??), as I have been running into a few problems, despite following the advice I could find in older mailing-list threads or the wiki. My goal would be to run a full-system with ruby (with MOESI_CMP_directory), mu

Re: [gem5-users] Set total order among multiple logic buses

Hmmm the ruby_network_tester is supposed to be used only with the NetworkTest coherence protocol … Not sure how it interacts with other protocols. With Hammer, I would suggest using ruby_random_test Don't know how controllers work with multiple input links. I think they should work fine. In any

Re: [gem5-users] Question on GARNET + Ruby

That is the combined power for entire NoC. If you want individual router power, and/or breakdown of individual components, look at network/orion/NetworkPower.cc - Tushar On Aug 28, 2012, at 12:30 PM, Pavan Poluri wrote: > Hello, > > I have done a full system simulation with 8 cores, 8 routers,

Re: [gem5-users] How to define Memory specification in Gem5?

Hi Andreas, Thanks for the info. When do you expect the DRAM controller model will be available? If it it going to take a while, is it possible for me to get an early release version for  testing? Thanks. Victor From: Andreas Hansson To: Victor Ling ; g

Re: [gem5-users] How to define Memory specification in Gem5?

Hi Victor, We are in the process of submitting a DRAM controller model to the review board. This will enable you to evaluate the impact of different DRAM organisations as you suggest. Stay tuned… Andreas From: Victor Ling mailto:victor_lin...@yahoo.com>> Reply-To: Victor Ling mailto:victor_l

Re: [gem5-users] Running Android on Gem5 - Creating custom Android image file

Thanks Anthony. I renamed the image file to contain the "android" word. Now there are no kernel panic messages. I have a few additional questions: 1. How long does the Android boot usually take? I have been running the simulation for about 2.5 hours now but the screen is still stuck on the Andro

Re: [gem5-users] ARM: data instructions writing to PC not set as control instructions

Hi Nathanaël, Sent from my ARM powered mobile device On Aug 28, 2012, at 11:34 AM, Nathanaël Prémillieu wrote: > Hi Ali, > > Thank for your response. > I was thinking that data instructions as branch was a specificity of ARMv7. > In The ARM Architecture Reference Manual, p. 170, it is stated

[gem5-users] Question on GARNET + Ruby

Hello, I have done a full system simulation with 8 cores, 8 routers, 8 L2 caches on a mesh topology with garnet's fixed pipeline implementation. The simulation statistics can be seen in ruby.stats file that contains router power statistics like router dynamic power, router static power, router clo

Re: [gem5-users] ARM: data instructions writing to PC not set as control instructions

Hi Ali, Thank for your response. I was thinking that data instructions as branch was a specificity of ARMv7. In The ARM Architecture Reference Manual, p. 170, it is stated that: "In ARMv7, a processor in ARM state can also enter Thumb state (and change to executing Thumb instructions) by execut

Re: [gem5-users] ARM: data instructions writing to PC not set as control instructions

Hi Nathanaël, The use of data instructions as branches is deprecated so we chose not to mark them as branches and I'd hope you're not seeing too much use of them. If you care the isBranch kwarg can be passed to the various data instructions in src/arch/arm/isa/insts/data.isa like it is for the

[gem5-users] self statically compiled SPLASH2 incorrect result on X86 FS Mode

Hi all, I compiled splash2 benchmarks (kernel part exactly ) statically on my own (x86-64 bit linux machine with 2.6.28-15 kernel and glibc 2.13 ,gcc 4.5.2) and put them on the disk img file. They got run without errors but results seems incorrect. Here comes details. All x86 full system staff (pr

Re: [gem5-users] ARM: data instructions writing to PC not set as control instructions

Hi All, Any thoughts on that matter ? Because not having these instructions identified as control instructions causes the branch predictor to not predict them, increasing the number of branch mispredictions. It seems that some load instructions have also this problem. Thanks, Nathanaël Le 2

Re: [gem5-users] Set total order among multiple logic buses

Actually Pt2Pt will also have a deadlock if the sim cycles are that many. On Tue, Aug 28, 2012 at 1:57 AM, gem5 gem5 wrote: > Hi Tushar, > > I wonder if all the nodes(controllers) need to have a router before them. > This is what I have seen for all the topologies created in GEM5. I have > t